Abstract: Provided are an apparatus and method for generating common locator bits to locate a device or column error during error correction operation for a memory subsystem having memory modules, each including a plurality of memory devices. Error detection logic generates common locator bits from device bits in a plurality of memory devices in one of the memory modules. The error detection logic uses the common locator bits to locate a column across at least two of the memory devices having an error when there is a column error and to locate a memory device in the devices having an error when there is a device error. A same of the common locator bits are used to locate both one of the columns and the memory devices having errors. Error correction is performed on the located memory device or column having the error.

Abstract: The present invention relates to a method of transmitting and a method of receiving signals an corresponding apparatus. One aspect of the present invention relates to an efficient L1 signaling method for an efficient transmitter and an efficient receiver using the efficient L1 signaling method for an efficient cable broadcasting.

Abstract: A parity error is detected in a header, where the header is in a particular one of a plurality of queues, the header is to include a plurality of fields, and each of the queues is to correspond to a respective transaction type. Fabricated header data is generated for one or more of the plurality of fields to indicate the parity error and replace data of one or more of the plurality of fields. An error containment mode is entered based on the parity error.

Abstract: A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

Abstract: Systems and methods are provided for quantum error correction. A quantum system includes an array of qubits configured to store an item of quantum information. The array of qubits includes a plurality of data qubits and a plurality of measurement qubits configured to extract a syndrome representing agreement among the plurality of data qubits. The quantum system further includes an integrated circuit comprising validation logic configured to determine if the syndrome is valid, decoding logic configured to determine evaluate the syndrome to determine location of errors within the plurality of data qubits, and an error register configured to store locations of the determined errors.

Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.

Abstract: A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.

Abstract: A method, apparatus, and chipset are provided for constructing hybrid automatic repeat request (HARQ) rate-compatible polar codes for communication channels. The method includes constructing, in a terminal, a base polar code of length 2n; and determining a sequence of m<2n bits to puncture in the base polar code by testing a predetermined criterion at most (22n+2n)/2?1 times.

Abstract: A residue-based error checking mechanism is provided for checking for error in a shift operation of a shifter. The checking includes: partitioning an input vector into the shifter into one or more bit groups of bit width W; generating a predicted residue on the input vector being shifted, the generating including masking out any bit group of bit width W fully shifted out by the shift operation from contributing to the predicted residue, and the generating accounting for any bits of a bit group of the input vector partially shifted out by the shift operation; generating a result residue on a result vector of the shift operation; and comparing the result residue with the predicted residue to check for an error in the result vector of the shift operation.

Abstract: A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.

Abstract: A transmission system for avionics application data is disclosed. In one aspect, the system is for transmitting avionics application data between data producing means and data consuming means, the application data being transmitted in the form of data transmission units, each including: at least one portion of an application message, and an additional message containing identification and control information. The additional message includes: an identification sequence including a static part making it possible to identify the application message and its source and a variable part making it possible to distinguish the message in a unique manner, and a control sequence designed to check the integrity of the application message and based on a sequence representing a cyclic redundancy control code of the concatenation of at least one portion of the application message corresponding to said unit, with the identification sequence.

Abstract: A receiving device includes a termination circuit to which a received signal is input, a processing circuit which performs a process at a rear stage of the termination circuit, and an error detection circuit which detects an error contained in the received signal. In a case where the error is detected by the error detection circuit, a termination resistance value of the termination circuit is lowered. Therefore, the receiving device can be rapidly restored when a signal containing an error is received.

Abstract: A data storage method is used to improve storage consistency of a distributed storage system. The method includes: a primary storage node performs EC coding on a to-be-stored data segment to obtain a target EC stripe; determines in a storage node group to which the primary storage node belongs, m+k target storage nodes used to store m+k target EC blocks of the target EC stripe; sends a preparation message to the target storage nodes; receives a response message sent by a target storage node; and sends an execution message to the target storage nodes to instruct the target storage nodes to write target EC blocks that are in preparation logs.

Abstract: Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system.

Abstract: A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. The device receives a non-binary low density parity check (NB-LDPC) coded signal. The device then decodes the NB-LDPC coded signal using a NB-LDPC matrix to generate estimates of information bits encoded therein. The NB-LDPC matrix is characterized by a base proto-matrix having elements that represent sub-matrices, and the elements are selected from a finite Galois field that includes symbols.

Abstract: A method and a device for removing pathologic error patterns in binary data are proposed. The method comprises the operations of identifying a pathologic error pattern in the binary data, and inverting all bits of the identified pathologic error pattern.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: An apparatus may comprise an ECC circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the read data responsive, at least in part, to a parity portion of the read data, to generate a plurality of first error determination signals and a plurality of second error determination signals. Each of the plurality of first error determination signals provided in common to n data terminals and corresponding to an associated one of burst data of m bits. Each of the plurality of second error determination signals provided in common to the burst data of m bits and corresponding to an associated one of the n data terminals. The error bit of the data portion of the read data is detected based, at least in part, on the first error determination signals and the second error determination signals.

Abstract: An aircraft communication system for performing communication between each of a plurality of devices installed in an aircraft, wherein the communication system is provided with a plurality of communication processing units provided corresponding to the plurality of devices and a plurality of communication lines for connecting between the communication processing units, the plurality of communication processing units being capable of bidirectional communication via the plurality of communication lines. Upon receiving a plurality of communication data from the plurality of communication lines, one of the communication processing units determines, on the basis of identification information included in the received plurality of communication data, whether the received plurality of communication data needs to be acquired and acquires the communication data determined to need to be acquired.

Abstract: In various embodiments, an apparatus, system, and method may increase data integrity in a redundant storage system. In one embodiment, a request is received for data stored at a storage system having a plurality of storage elements, where one or more of the plurality of storage elements include parity information. A determination is made that one of the plurality of storage elements is unavailable, the unavailable storage element being a functional storage element and including at least a portion of the data. Responsive to the determination, the data is reconstructed based on at least a portion of the parity information and data from one or more of the plurality of storage elements other than the unavailable storage element; a response is provided to the request such that the response includes the reconstructed data.