Patents Examined by Esaw T Abraham
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Patent number: 11626889Abstract: Iterative signal processing. At communication hardware, a signal is received from a transmission medium. The signal has characteristics that obscure data or a signal of interest in the signal. The signal is processed at a first signal processor, which is an iterative processor that performs signal processing in cycles whereby successive cycles: improve the performance of processing of the processor itself over previous cycles, or improve the output from the processor. The signal is processed at one or more second signal processors. Extrinsic data, with respect to the first signal processor is produced as a result. The extrinsic data is provided to the first signal processor and used to counter the effects of the data or signal of interest being obscured in the signal, while the first signal processor is intracycle of a first processing cycle.Type: GrantFiled: November 16, 2021Date of Patent: April 11, 2023Assignee: L3HARRIS TECHNOLOGIES, INC.Inventors: Ryan W. Hinton, David G. Landon, Joshua D. Gunn
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Patent number: 11626168Abstract: Systems and methods of the present disclosure may be used to improve equalization module architectures for NAND cell read information. For example, embodiments of the present disclosure may provide for de-noising of NAND cell read information using a Multiple Shallow Threshold-Expert Machine Learning Models (MTM) equalizer. An MTM equalizer may include multiple shallow machine learning models, where each machine learning model is trained to specifically solve a classification task (e.g., a binary classification task) corresponding to a weak decision range between two possible read information values for a given NAND cell read operation. Accordingly, during inference, each read sample with a read value within a weak decision range is passed through a corresponding shallow machine learning model (e.g., a corresponding threshold expert) that is associated with (e.g., trained for) the particular weak decision range.Type: GrantFiled: March 10, 2021Date of Patent: April 11, 2023Assignee: SAMSUNG ELECTRONICS CO.. LTD.Inventors: Amit Berman, Evgeny Blaichman, Ron Golan, Sergey Gendel
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Patent number: 11625296Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.Type: GrantFiled: May 13, 2021Date of Patent: April 11, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Hyun-Joong Kim, Won-hyung Song, Jangseok Choi
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Patent number: 11616515Abstract: Disclosed are a method and an apparatus for fast decoding a linear code based on soft decision. The method may comprise sorting received signals in a magnitude order to obtain sorted signals; obtaining hard decision signals by performing hard decision on the sorted signals; obtaining upper signals corresponding to MRBs from the hard decision signals; obtaining a permuted and corrected codeword candidate using the upper signals and an error vector according to a current order; calculating a cost for the current order using a cost function; determining the permuted and corrected codeword candidate as a permuted and corrected codeword according to a result of comparing the calculated cost with a minimum cost; and determining a predefined speeding condition.Type: GrantFiled: September 20, 2021Date of Patent: March 28, 2023Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Chang Ryoul Choi, Je Chang Jeong
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Patent number: 11606169Abstract: Disclosed herein includes a system, a method, and a device for prioritizing packet retransmission. A transmitting device can insert, for each packet of a plurality of packets of a video frame, a sequence number indicative of an order of the corresponding packet among the plurality of packets, into a header of the corresponding packet according to an application layer protocol. The transmitting device can transmit to the receiving device, at a first level of priority, the plurality of packets including the corresponding inserted sequence numbers. The transmitting device can receive an identification of one or more packets to be retransmitted to the receiving device, the identification based on at least the inserted sequence numbers of the one or more packets. The transmitting device can retransmit the one or more packets at a second level of priority that is higher than the first level of priority.Type: GrantFiled: September 3, 2021Date of Patent: March 14, 2023Assignee: Meta Platforms Technologies, LLCInventors: Behnam Bastani, Xiaoguang Wang, Gang Lu
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Patent number: 11606105Abstract: Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.Type: GrantFiled: November 17, 2021Date of Patent: March 14, 2023Assignee: Western Digital Technologies, Inc.Inventors: Jun Tao, Niang-Chu Chen
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Patent number: 11601140Abstract: Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for improving communication throughput despite periodic blockages. In some implementations, a method includes receiving, by a receiver and from a transmitter, code blocks transmitted according to a first set of communication parameters that includes one or more first interleaver parameters used to interleave information in the code blocks prior to transmission. Corrupted portions of at least some of the received code blocks are identified. A blockage duration and a blockage interval of a blockage of communication channel between the transmitter and the receiver are determined based on the corrupted portions of the received code blocks. A second set of communication parameters that includes one or more second interleaver parameters are determined based on the blockage duration and blockage interval.Type: GrantFiled: December 29, 2021Date of Patent: March 7, 2023Assignee: Hughes Network Systems, LLCInventor: Victor Liau
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Patent number: 11601141Abstract: Apparatuses, systems, and methods are presented for error correction based on physical characteristics for memory. A controller may be configured to read a set of encoded bits from a set of cells of a memory array. The controller may be configured to divide the encoded bits into reliability groups based on one or more persistent physical characteristics associated with cells of the set of cells. The controller may be configured to provide reliability estimates based on the reliability groups to a soft decision decoder for decoding the encoded bits.Type: GrantFiled: February 26, 2021Date of Patent: March 7, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Gadi Vishne, David Rozman, Alex Bazarsky
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Patent number: 11601220Abstract: A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.Type: GrantFiled: May 28, 2021Date of Patent: March 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
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Patent number: 11593203Abstract: A method for proactively rebuilding user data in a plurality of storage nodes of a storage cluster is provided. The method includes distributing user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can read the user data, using erasure coding, despite loss of two of the storage nodes. The method includes determining that one of the storage nodes is unreachable and determining to rebuild the user data for the one of the storage nodes that is unreachable. The method includes reading the user data across a remainder of the plurality of storage nodes, using the erasure coding and writing the user data across the remainder of the plurality of storage nodes, using the erasure coding. A plurality of storage nodes within a single chassis that can proactively rebuild the user data stored within the storage nodes is also provided.Type: GrantFiled: May 21, 2021Date of Patent: February 28, 2023Assignee: Pure Storage, Inc.Inventors: John Martin Hayes, John Colgrove, Robert Lee, Igor Ostrovsky, Joshua P. Robinson
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Patent number: 11581052Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a plurality of storage areas. Each of the storage areas includes a plurality of memory cells to which threshold voltages are set in accordance with data. The controller acquires a first threshold voltage distribution of memory cells in a first storage area of the storage areas. The controller acquires a second threshold voltage distribution of memory cells in a second storage area of the storage areas. The controller detects non-normalcy in the first storage area or the second storage area from a first divergence quantity between the first threshold voltage distribution and the second threshold voltage distribution.Type: GrantFiled: September 3, 2020Date of Patent: February 14, 2023Assignee: Kioxia CorporationInventors: Akiyoshi Hashimoto, Makoto Kuribara, Takeshi Tomizawa, Katsuhiko Ueki
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Patent number: 11575464Abstract: The present invention related to a 5G or pre-5G communication system to be provided to support a higher data transmission rate since 4G communication systems like LTE. The present invention relates to a method and an apparatus for encoding a channel in a communication or broadcasting system supporting parity-check matrices having various sizes are provided. The method for encoding a channel includes determining a block size of the parity-check matrix; reading a sequence for generating the parity-check matrix, and transforming the sequence by applying a previously defined operation to the sequence based on the determined block size.Type: GrantFiled: June 21, 2021Date of Patent: February 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Seho Myung, Kyungjoong Kim, Min Jang, Hongsil Jeong
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Patent number: 11568926Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.Type: GrantFiled: November 23, 2020Date of Patent: January 31, 2023Assignee: Arm LimitedInventors: Andy Wangkun Chen, Teresa Louise McLaurin, Frank David Frederick, Richard Slobodnik, Yew Keong Chong
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Patent number: 11563516Abstract: Methods and systems for operation in a wireless communication system are provided. A first transmission may be initiated using at least a first portion of physical layer resources. A second transmission may be initiated using at least a second portion of the same physical layer resources. The first transmission may be any one of a puncturing transmission, interfering transmission, delay-sensitive transmission, or short transmission. The second transmission may be an on-going transmission or a long transmission.Type: GrantFiled: September 22, 2020Date of Patent: January 24, 2023Assignee: IDAC Holdings, Inc.Inventors: Paul Marinier, Ghyslain Pelletier, Benoit Pelletier
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Patent number: 11556416Abstract: An apparatus for data storage includes an interface and a processor. The interface is configured to communicate with a memory device that includes (i) a plurality of memory cells and (ii) a data compression module. The processor is configured to determine a maximal number of errors that are required to be corrected by applying a soft decoding scheme to data retrieved from the memory cells, and based on the maximal number of errors, to determine an interval between multiple read thresholds for reading Code Words (CWs) stored in the memory cells for processing by the soft decoding scheme, so as to meet following conditions: (i) the soft decoding scheme achieves a specified decoding capability requirement, and (ii) a compression rate of the compression module when applied to confidence levels corresponding to readouts of the CWs, achieves a specified readout throughput requirement.Type: GrantFiled: December 22, 2021Date of Patent: January 17, 2023Assignee: APPLE INC.Inventors: Nir Tishbi, Itay Sagron
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Patent number: 11557353Abstract: An optimal detection voltage obtaining method, a reading control method and an apparatus are provided.Type: GrantFiled: December 9, 2021Date of Patent: January 17, 2023Assignee: MAXIO TECHNOLOGY (HANGZHOU) CO., LTD.Inventors: Xuhang Zhang, Xiaofan Yu, Zihua Xiao, Ye Jin, Quan Cai, Xiaomin Luo, Lihong Zhao, Rui Cao
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Patent number: 11558148Abstract: An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.Type: GrantFiled: June 11, 2021Date of Patent: January 17, 2023Assignee: NOKIA SOLUTIONS AND NETWORKS OYInventors: Keeth Saliya Jayasinghe Laddu, Yi Zhang, Jingyuan Sun
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Patent number: 11552653Abstract: A quantum decoder receives a syndrome from a quantum measurement circuit and performs various decoding operations for processing-efficient fault detection. The decoding operations include generating a decoding graph from the syndrome and growing a cluster around each one of multiple check nodes in the graph that correspond to a non-trivial value in the syndrome. Each cluster includes the check node corresponding to the non-trivial value and a set of neighboring nodes positioned within a distance of d edge-lengths from the check node. Following cluster growth, the decoder determines if, for each cluster, there exists a solution set internal to the cluster that fully explains the non-trivial syndrome bit for the cluster. If so, the decoder identifies and returns at least one solution set that fully explains the set of non-trivial bits in the syndrome.Type: GrantFiled: February 26, 2021Date of Patent: January 10, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Nicolas Guillaume Delfosse, Michael Edward Beverland, Vivien Londe, Jeongwan Haah
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Patent number: 11550663Abstract: Systems and methods are disclosed that are of retrieving, by a processing device, a codeword stored at a memory sub-system, determining parity data of the codeword, generating additional parity bits based on one or more bits of the parity data of the codeword, and generating host data by decoding the codeword using the additional parity bits.Type: GrantFiled: February 22, 2021Date of Patent: January 10, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Tingjun Xie, Ying Yu Tai, Jiangli Zhu
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Patent number: 11531472Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.Type: GrantFiled: April 27, 2021Date of Patent: December 20, 2022Assignee: Micron Technology, Inc.Inventor: J. Thomas Pawlowski