Abstract: A delay circuit comprises a tapped delay element line constructed from delay elements with fixed delay intervals and a multiplexer for selecting the signal at one of the taps to produce a variable delay through the circuit. The multiplexer is controlled by a selection circuit which receives an input indicative of the actual delay time through the delay circuit from an oscillator constructed from the same fixed delay elements as the delay line.

Abstract: An adjustable timer circuit capable of producing accurate pulse outputs having a wide range of periods. The timer circuit includes a timing capacitor and an associated current source for producing a reference current having a magnitude which is derived from a reference voltage. A current divider is used to divide the reference current down to a smaller current used for charging the timing capacitor. A comparator circuit is provided for comparing the voltage produced across the timing capacitor with a comparison voltage also derived from the reference voltage. The timing capacitor is discharged in response to the comparator output so that subsequent output pulses can be produced. The current divider is adjustable in response to a mode control signal so that different magnitude charging currents can be produced which results in different magnitude pulse width outputs.

Abstract: A wideband level shift circuit (200) used with low voltage ECL or CML topologies includes a sub-Vbe voltage reference (201) whose output voltage is offset some fraction of a diode voltage drop below a supply voltage, where the fraction is held at a constant value as the diode voltage varies with temperature. A comparator circuit (203) is attached to the reference voltage circuit (201) as well as to a current sourcing transistor and differential buffer circuit (205). The comparator circuit (203) maintains the DC potential at the output of a current sourcing transistor so that the common-mode DC level of the output signal from a differential buffer is shifted down by a fraction of a diode drop from the common-mode DC level of a wideband AC input signal. The shift circuit (200) offers the advantages of a fraction of a diode DC voltage drop with little loss of AC signal bandwidth for circuits operating from low supply voltages.

Abstract: According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.

Abstract: An apparatus for monitoring a reference clock signal having a clock pulse train comprises a detecting block for counting pluses of a count clock signal to produce a count value and generate a count failure signal when the count value reaches a predetermined value, wherein the frequency of the count clock signal is larger than that of the reference clock signal; and a controlling block for generating a clear signal at every clock pulse of the reference clock signal to cleat the detecting block when the clear signal is inputted thereto.

Abstract: A circuit and method are shown for a continuously adjustable delay circuit. The present invention utilizes two signal delay paths controlled by a tuning signal wherein each delay path receives a reference signal. The first delay path delays the reference signal in response to the tuning signal in a manner that is complementary to the manner in which the second delay path delays the reference signal in response to the tuning signal. By selecting one of the signal output by the first delay path and the signal output by the second delay path and switching between the two signals at a point when the two signals are separated by a period of the reference signal, a delay of the reference signal can be continuously adjusted.

Abstract: A circuit and method for compensating for the output phase delay of an external clock signal utilizes a phase-locked loop that includes an output port of an integrated circuit device. In the phase-locked loop, a phase detecting circuit compares the external clock signal with an output signal from the output port, producing a phase error signal. The phase error signal is applied to a skew compensator to generate an internal clock signal. The internal clock signal is fed back through the output port to the phase detecting circuit. Clock jitter is reduced by reducing the gain of the skew compensator after a phase lock condition occurs in the compensation circuit.

Abstract: Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (31.sub.0 -31.sub.n, 32.sub.0 -32.sub.n, 33.sub.0 -33.sub.n, 34.sub.0 -34.sub.n) coupled thereto which, in response to a control signal (b.sub.0 -b.sub.n) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a first embodiment, the control signals (b.sub.0 -b.sub.n) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (47.sub.0 -47.sub.n) and the capacitors (53.sub.0 -53.sub.n), respectively, are coupled in a capacitance charging circuit (47.sub.0 -47.sub.n, 43; 52, 53.sub.0 -53.sub.n), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus.

Abstract: An output signal is output to a selected one of first and second output nodes in response to an event in which a control node transitions from a first logic state to a second logic state. The selected one of the first and second output nodes is selected in response to a logic state of an input node during the event. A minimum setup time for the logic state of the input node to be stable before the control node transitions to the second logic state is shorter than a minimum time for inverting the logic state of the input node.

Abstract: A closed loop clock delay adjustment system measures the drift between the delay introduced by clock buffers and by delays inserted at the device data input pins. The system uses a reference delay at the input of a measurement flip-flop. The reference delay is defined to be an approximate average of the delays at the data input pins. An external clock signal is coupled to the input of the reference delay. The output of the reference delay is coupled to the data input of the measurement flip-flop. The external clock signal is also coupled to the input of a variable clock delay buffer sub-circuit. The output of the variable clock delay buffer is coupled to the clock signal input of the measurement flip-flop. In operation, the measurement flip-flop compares the variable clock delay buffer output signal with the clock signal delayed by the reference delay. If the variable clock delay buffer output signal is delayed more than the reference delay output signal, the variable clock delay is decreased.

Abstract: A dual phase synchronous race delay clock circuit that will create an internal clock signal in an integrated circuit that is synchronized with and has minimum skew from an external system clock signal is disclosed. The synchronous race delay circuit has an input buffer circuit to receive, buffer, and amplify an external clock signal. The input buffer circuit has a delay time that is the first delay time. A fast pulse generator is connected to the input buffer circuit to create a fast pulse signal. The fast pulse generator is connected to a slow pulse generator to create a slow pulse signal. The fast pulse generator and the slow pulse generator is connected to a race delay measurement means to determine a measurement of a period of the external system clock by comparing a time difference between the slow pulse signal and a following fast pulse signal. A delay control means is connected to the race delay measurement means to receive the measurement of the period of the external system clock.

Abstract: It is an object to obtain a semiconductor device capable of changing a delay time of an output signal of a PLL circuit with respect to an external clock signal after installed in a system. An external clock signal is inputted to an input terminal (1.) An address value is inputted to an input terminal (3.) A decoder (9) selects one of a plurality of delay times in a voltage-controlled oscillator (8) according to the address value. The phase of a signal outputted to an output terminal (2) is delayed with respect to the external clock signal at the input terminal (1) by the delay time selected. Accordingly, it is possible to change the delay time of the output signal of the PLL circuit with respect to the external clock signal after installation in a system.

Abstract: By using a bias switch (260) to define a unique current range in a bias generator (142) for each n-bit counter output state, it is possible to control a VCO (140) which has a very wide operating frequency range. These frequency ranges must overlap to guarantee the lock irrespective of process or environmental (temperature and voltage) variations. Depending on an input value of an overall lock signal OLS to an n-bit counter (250) at the rising edge of its clock signal CLK, it is possible to scan the full spectrum of VCO frequency ranges until the lock is achieved. By comparing a switch voltage to a reference voltage Vref, it is possible to prevent the PLL from locking at the very right-hand edge of a frequency range unless it can maintain that the lock over the entire operating temperature range. By strobing a fine lock signal FLS at an integer m (>1) number of points, it is possible to prevent false lock from occurring.

Abstract: A delay element including a stack of p-channel transistors connected in series and a stack of n-channel transistors connected in series with the source of the top p-channel transistor connected to a positive voltage and the source of the bottom n-channel transistor connected to ground. The drain of each n-channel transistor is connected to the drain of a corresponding one of the p-channel transistors and all gates are interconnected and serve as the input to the delay element. The output of the delay element can be any one of the drain connections.

Abstract: The present invention provides a phase locked loop (PLL) clock generator for a digital system. The PLL clock generator is capable of an instantaneous transition between a high frequency and a low frequency, corresponding to an active mode and a slow mode, and vice versa The PLL clock generator includes a phase locking circuit, a frequency changer coupled to the output of the phase locking circuit, and a frequency controller coupled to the frequency changer. The frequency changer is capable of instantaneously changing the frequency of a first clock signal received from the phase locking circuit. The frequency controller is responsible for controlling the frequency at the output of the frequency changer. The frequency controller is responsive to a control signal which is used to transition the PLL clock generator from an active mode to a slow mode and vice versa In one embodiment, the phase locking circuit generates the first clock signal in response to a reference clock signal and a feedback clock signal.

Abstract: A variable delay circuit for a semiconductor memory device includes an input buffer for converting a digital input signal to an analog signal and buffering the resultant analog signal, an analog delay unit for delaying the analog signal outputted from the input buffer unit for a certain time, and an output buffer unit for converting the delayed analog signal to a digital signal and buffering the resultant digital signal. The analog delay unit is composed of a CMOS inverter, a plurality of operational transconductance amplifier-capacitor delay elements, and an output inverter, to form a second-order Bessel filter. An O.T.A and an inverter may be additionally provided between the plurality of O.T.A.'s for thereby decreasing a parasitic effect of the capacitors connected to the outputs of each of the plurality of O.T.A.'s in the analog delay unit.

Abstract: There is provided an adjustment circuit which delays a first and a second signal by a desired delay. After the first and the second signal are inputted to the adjustment circuit via a first and a second signal line, respectively, the first and the second signal are exchanged and are inputted via the second and the first signal line, respectively. A detection circuit receives the first and the second signal from the adjustment circuit, and detects the phase differences of these signals, before and after the exchange. The holding circuit holds a first phase difference detected by the detection circuit before the exchange, and holds a second phase difference detected by the detection circuit after the exchange. When the holding circuit holds the first and the second phase difference, a comparison circuit compares these phase differences. A counter counts in accordance with the comparison results of the comparison circuit, and sets the desired delay of the adjustment circuit.

Abstract: A phase/frequency detector, such as may be used in a phase-lock loop (PLL), having reduced jitter at high frequencies by reducing or eliminating the dead zone. The detector generates two output signals (UP and DOWN) wherein one of the output signals (depending upon which input signal arrives first) has a pulse width which is equal to a time delay between the input signals. There is a dead zone associated with very small phase differences between the input signals, and the dead zone is reduced by increasing the durations of two output pulses, using several delay elements which operate on signals that are derived from the reference and feedback inputs. The circuit may be tuned to reduce the dead zone to less than one picosecond, making it particularly useful for very high speed (greater than one gigahertz) clock circuits. The phase/frequency detector uses self-resetting, complementary metal-oxide semiconducting (SRCMOS) gates.

Abstract: A delay circuit having standby state and active state and designed to output at least one signal obtained by delaying an input signal. The delay circuit comprises a storage circuit and at least one amplifier circuit. In operation, the storage circuit receives an input signal, generates a first voltage when the input signal is inverted, and generates a second voltage from a difference between the first voltage and a first supply voltage. The amplifier circuit amplifies the difference between the first voltage and the second voltage.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.