Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Abstract: A semiconductor device may include a semiconductor layer having a first conductivity type, a well region of a second conductivity type in the semiconductor layer wherein the first and second conductivity types are different, and a terminal region of the first conductivity type in the well region. An epitaxial semiconductor layer may be on the surface of the semiconductor layer including the well region and the terminal region with the epitaxial semiconductor layer having the first conductivity type across the well and terminal regions. A gate electrode may be on the epitaxial semiconductor layer so that the epitaxial semiconductor layer is between the gate electrode and portions of the well region surrounding the terminal region at the surface of the semiconductor layer.

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

Abstract: A light-emitting device according to an aspect of the present disclosure includes a light transmissive first electrode layer, a light transmissive second electrode layer, an electroluminescent layer between the first electrode layer and the second electrode layer, and a reflective layer located on a side opposite to the electroluminescent layer with respect to the second electrode layer. The reflective layer includes a base material having a refractive index equal to or higher than a refractive index of the electroluminescent layer, and fillers each having a refractive index different from that of the base material.

Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.

Abstract: A lateral p-n diode in the center of and surrounded by a vertical Silicon-Controlled Rectifier (SCR) forms an Electro-Static-Discharge (ESD) protection structure. The lateral p-n diode has a cross-shaped P+ diode tap with four rectangles of N+ diode regions in each corner of the cross. A P-well under the P+ diode tap is also an anode of a vertical PNPN SCR that has a deep N-well in a P-substrate. The deep N-well surrounds the lateral diode. Triggering MOS transistors are formed just beyond the four ends of the cross shaped P+ diode tap. Each triggering MOS transistor has N+ regions at the edge of the deep N-well and in the P-substrate that act as the cathode terminals. A deep P+ implant region under the N+ region at the edge of the deep N-well decreases a trigger voltage of the vertical SCR.

Abstract: A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, and elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements. The conductive nanoparticles can be disposed between the surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers.

Abstract: A display substrate and a method for repairing a lead of a driver integrated circuit. The display substrate comprises: multiple signal leads on the display substrate, at least one driver integrated circuit, at least one repair chip (RC), at least one repair lead, and at least one repair line (13). The RC is connected to the at least one driver integrated circuit, the repair lead is connected to the RC, and the repair line crosses signal lines connected to multiple signal leads, and is insulated from the signal lines. When the signal leads connected to the driver integrated circuit is in poor contact, the repair lead and the repair line (13) are used to replace the signal lead in poor contract, which solves a problem that an existing display substrate cannot repair a signal lead in poor contact in an outer lead region, causing wastes of products, and improving costs of the products.

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

Abstract: A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.

Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.

Abstract: The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact.

Abstract: According to an embodiment, the invention provides an nFET/pFET pair of finFETs formed on a gate stack. At least one fin extends into a source drain region of each of the FET pair and a carbon doped silicon (Si:C) layer is formed on each such fin. Another aspect of the invention is a process flow to enable dual in-situ doped epitaxy to fill the nFET and pFET source drain with different epi materials while avoiding a ridge in the hard cap on the gate between the pair of finFETS. The gate spacer in both of the pair can be the same thickness. The extension region of both of the pair of finFETs can be activated by a single anneal.

Abstract: Techniques for forming nanostructured materials are provided. In one aspect of the invention, a method for forming nanotubes on a buried insulator includes the steps of: forming one or more fins in a SOI layer of an SOI wafer, wherein the SOI wafer has a substrate separated from the SOI layer by the buried insulator; forming a SiGe layer on the fins; annealing the SiGe layer under conditions sufficient to drive-in Ge from the SiGe layer into the fins and form a SiGe shell completely surrounding each of the fins; and removing the fins selective to the SiGe shell, wherein the SiGe shell which remains forms the nanotubes on the buried insulator. A nanotube structure and method of forming a nanotube device are also provided.

Abstract: A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned dielectric layer atop the Kelvin-contact source and the trench gate; a patterned top metal layer. As a result: a planar ledge is formed atop the Kelvin-contact source; the MOSFET device exhibits a lowered body Kelvin contact impedance and, owing to the presence of the planar ledge, a source Kelvin contact impedance that is lower than an otherwise MOSFET device without the planar ledge; and an integral parallel Schottky diode is also formed.

Abstract: In a light-emitting element 1, a light-emitting layer 4, a second conductivity type semiconductor layer 5, a transparent electrode layer 6, a reflecting electrode layer 7 and an insulating layer 8 are stacked in this order on a first conductivity type semiconductor layer 3, while a first electrode layer 10 and a second electrode layer 12 are stacked on the insulating layer 8 in an isolated state.

Abstract: A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.

Abstract: A magnetic tunnel junction cell includes a first electrode having an axis extending in a direction substantially perpendicular to an active surface of a substrate. The magnetic tunnel junction further includes a fixed layer, a U-shaped free layer, a tunnel layer sandwiched between the fixed layer and the U-shaped free layer and a second electrode embedded in the U-shaped free layer. The fixed layer, the tunnel layer and the U-shaped free layer are disposed between the first electrode and the second electrode and constitute a magnetic tunnel junction. The tunnel layer may also be U-shaped.

Abstract: A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

Abstract: A process for fabricating an integrated circuit package includes selectively etching a leadframe strip to define a die attach pad and a plurality of contact pads. At least one side of the die attach pad has a plurality of spaced apart pad portions. A semiconductor die is mounted to the die attach pad and wires are bonded from the semiconductor die to respective ones of the contact pads. A first surface of the leadframe strip, including the semiconductor die and wire bonds, is encapsulated in a molding material such that at least one surface of the leadframe strip is exposed. The integrated circuit package is singulated from a remainder of the leadframe strip.