Patents Examined by Fernando L. Toledo
  • Patent number: 11043562
    Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: June 22, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11043647
    Abstract: The present disclosure relates to a quantum dot film including a self-assembled block copolymer, and a quantum dot bonded to the block copolymer, wherein the film has pores with an average diameter of 100-3000 nm inside.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: June 22, 2021
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yeon Sik Jung, Duk Young Jeon, Geon Yeong Kim, Jin Young Choi, Chul Hee Lee, Hun Hee Lim
  • Patent number: 11043542
    Abstract: An organic light-emitting display panel and a display device are provided. The organic light-emitting display panel includes: a driving device film layer, an anode layer, a pixel definition layer, an organic light-emitting layer, a cathode layer, an encapsulation film layer, and a touch film layer that are sequentially stacked. The encapsulation film layer includes an organic encapsulation layer. The organic light-emitting display panel has a specially-shaped border area and a straight-line border area. In the cathode connection area, in a direction perpendicular to the organic light-emitting display panel, a top end of the cathode layer is higher in the specially-shaped border area than in the straight-line border area, and the top end of the cathode layer is an end of the cathode layer furthest away from the driving device film layer.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 22, 2021
    Assignee: WuHan TianMa Micro-electronics CO., LTD
    Inventors: Guofeng Zhang, Zhaokeng Cao, Linshan Guo, Tianqing Hu
  • Patent number: 11043585
    Abstract: Reliability of a semiconductor device is improved. The semiconductor device including a first MISFET group of a plurality of first MISFETs and a second MISFET group of a plurality of second MISFETs has a plurality of trenches each formed in a semiconductor layer and formed of an upper trench part and a lower trench part, and a plurality of gate electrodes formed inside the plurality of trenches. A thinner gate insulator is formed to the upper trench part and a thicker field insulator is formed to the lower trench part. In a trench at the outermost position in the first MISFET group and a trench at the outermost position in the second MISFET group, the gate insulator is not formed in the upper trench part, but the field insulator is formed in the upper trench part and the lower trench part.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: June 22, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Wataru Sumida
  • Patent number: 11036320
    Abstract: An organic light emitting diode (OLED) folding display including a back plater, a base substrate, a thin film transistor array layer, an OLED device layer, a thin film encapsulation layer, and a laminated structure sequentially disposed are provided. The laminated structure includes a touch layer including a first touch metal layer and a second touch metal layer, a color filter layer disposed between the first touch metal layer and the second touch metal layer, and a black matrix layer disposed on the first touch metal layer. Use of the adhesive layer is reduced, and an influence of a bending stress of the OLED folding display is improved.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: June 15, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Peng Wang
  • Patent number: 11038100
    Abstract: A magnetoresistive element comprises a perpendicular coupling layer between a novel perpendicular AFM layer and ferromagnetic recording layer. The perpendicular coupling layer introduces giant magnetic anisotropy energies (P-MAE) on the recording layer interface and the P-AFM layer interface which further introduce RKKY coupling between the magnetic moment of the recording layer and the P-MAE induced magnetic moment at the P-AFM layer interface, yielding a giant perpendicular magnetic anisotropy of the recording layer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: June 15, 2021
    Inventor: Yimin Guo
  • Patent number: 11037979
    Abstract: An imaging element has at least a photoelectric conversion section, a first transistor TR1, and a second transistor TR2, the photoelectric conversion section includes a photoelectric conversion layer, a first electrode, and a second electrode, the imaging element further has a first photoelectric conversion layer extension section, a third electrode, and a fourth electrode, the first transistor TR1 includes the second electrode that functions as one source/drain section, the third electrode that functions as a gate section, and the first photoelectric conversion layer extension section that functions as the other source/drain section, and the first transistor TR1 (TRrst) is provided adjacent to the photoelectric conversion section.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 15, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Fumihiko Koga
  • Patent number: 11031335
    Abstract: Semiconductor devices may include a substrate and a redistribution layer. The redistribution layer may include a dielectric material and electrically conductive material. Vias may extend through the dielectric material. A first region of the electrically conductive material may be connected to a first subset of vias in a row from a first lateral side of the row, the first region occupying more than half of a width of the row on the first lateral side. A second region of the electrically conductive material may be connected to a second subset of vias in the row from a second, opposite lateral side of the row, the second region occupying more than half of the width of the row on the second lateral side.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hirokazu Ato, Koji Yasumori
  • Patent number: 11024574
    Abstract: Described is an apparatus which comprises: a die with a first side; a first set of solder balls coupled to the die along the first side; a laminate based substrate adjacent to the first set of solder balls, the laminate based substrate having at least one balun, at least one bandpass filter (BPF), and at least one diplexer embedded in the laminate, wherein the at least one balun is communicatively coupled to the first die via at least one of the solder balls of the first set.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventor: Sidharth Dalmia
  • Patent number: 11019291
    Abstract: A solid-state imaging device including a plurality of pixels including a photoelectric conversion portion, a charge holding portion accumulating a signal charge transferred from the photoelectric conversion portion, and a floating diffusion region to which the signal charge of the charge holding portion is transferred, wherein the photoelectric conversion portion includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type formed under the first semiconductor region, the charge holding portion includes a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type formed under the third semiconductor region, and a p-n junction between the third semiconductor region and the fourth semiconductor region is positioned deeper than a p-n junction between the first semiconductor region and the second semiconductor region.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: May 25, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masahiro Kobayashi, Takeshi Ichikawa, Hirofumi Totsuka, Yusuke Onuki
  • Patent number: 11018091
    Abstract: A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die, and a bottom dielectric layer over the device die and the molding material. A plurality of redistribution lines (RDLs) extends into the bottom dielectric layer and electrically coupling to the device die. A top polymer layer is over the bottom dielectric layer, with a trench ring penetrating through the top polymer layer. The trench ring is adjacent to edges of the package. The package further includes Under-Bump Metallurgies (UBMs) extending into the top polymer layer.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 11018073
    Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Wensen Hung, Hung-Chi Li, Tsung-Yu Chen
  • Patent number: 11011602
    Abstract: Circuits employing an adjacent low-k dummy gate to a field-effect transistor (FET) to reduce FET source/drain parasitic capacitance, and related fabrication methods. To reduce or mitigate an increase in the source/drain parasitic capacitance(s) of a FET, a dummy gate adjacent to an active gate of the FET is provided to have a low-k (i.e., low relative permittivity). In this manner, the relative permittivity (k) between the source/drain of the FET and an adjacent dummy gate and/or source/drain of another FET is reduced, thereby reducing the parallel plate capacitance of the FET(s). Reducing parasitic capacitance of the FET(s) may allow further reduced scaling of the circuit to offset or mitigate a lack of reduction or increase in parasitic capacitance as a result of reducing gate pitch in the circuit. As gate pitch is reduced in the circuit, it may not be possible to proportionally reduce gate size without sacrificing gate control.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 18, 2021
    Assignee: QUALCOMM Incorporated
    Inventor: Haining Yang
  • Patent number: 11009753
    Abstract: A display device includes a substrate, a first wiring and a second wiring positioned on the substrate, a thin film transistor (“TFT”) connected to the first wiring and the second wiring, and a pixel electrode connected to the TFT and including a transverse branch part, a longitudinal branch part, minute branches extending from the transverse branch part and the longitudinal branch part, and an outer branch part connecting end parts of the minute branches and adjacent to the storage electrode line, where a shortest distance from a center part of at least one side of the outer branch part to at least one side of the first wiring is different from a shortest distance from an edge part of at least one side of the outer branch part to at least one side of the first wiring.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Cheol Shin, Hak Sun Chang, Se Hyun Lee, Seung Min Lee
  • Patent number: 11011641
    Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta Wu, Cheng-Wei Chen, Shiu-Ko Jangjian, Ting-Chun Wang
  • Patent number: 11011477
    Abstract: A high-reliability electronic packaging structure includes a plurality of packaging layers and mechanical support layers. An electrically functional solder joint is provided in a first area of each of the packaging layers, and any two adjacent packaging layers are coupled using electrically functional solder joints. A mechanical support layer is disposed in a second area of each of the packaging layers, and the mechanical support layer is configured to support the two adjacent packaging layers. The first area is provided on a periphery of the second area. Hence, a problem that an internal silicon chip at an upper packaging layer or a lower packaging layer fractures and fails when the upper packaging layer or the lower packaging layer is subject to a mechanical load can be resolved.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 18, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hongbin Shi, Runqing Ye, Haohui Long
  • Patent number: 11004981
    Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 11, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soonmoon Jung, Daewon Ha, Sungmin Kim, Hyojin Kim, Keun Hwi Cho
  • Patent number: 11004887
    Abstract: A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, and a color filter disposed over the pixel sensor. The pixel sensor includes a plurality of first micro structures disposed over the back side of the substrate. The color filter includes a plurality of second micro structures disposed over the back side of the substrate. Each of the first micro structures has a first height, and each of the second micro structures has a second height. The second height is less than the first height.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Chieh Chiang, Keng-Yu Chou, Chun-Hao Chuang, Wen-Hau Wu, Jhy-Jyi Sze, Chien-Hsien Tseng, Kazuaki Hashimoto
  • Patent number: 11004729
    Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Gun Liu, Chin-Hsiang Lin, Chih-Ming Lai, Wei-Liang Lin, Yung-Sung Yen
  • Patent number: 10998407
    Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: May 4, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll