Patents Examined by Fernando L. Toledo
  • Patent number: 11849614
    Abstract: An organic light emitting diode display includes a lower substrate, a sub-pixel structure, an upper substrate, a sealant, and a first power supply wire. The lower substrate has a display area, a peripheral area, and a pad area. The sub-pixel structure is disposed in the display area on the lower substrate. The upper substrate is disposed on the sub-pixel structure. The sealant is disposed in the peripheral area between the lower substrate and the upper substrate. The first power supply wire is disposed between the lower substrate and the sealant, and overlaps the lower substrate and the sealant. The first power supply wire includes a first protrusion protruding in a first direction that is a direction from the pad area to the display area in the first peripheral area.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: December 19, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Bongwon Lee, Yanghee Kim, Hyun-Chol Bang, Sujin Lee
  • Patent number: 11848233
    Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.
    Type: Grant
    Filed: March 27, 2022
    Date of Patent: December 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Bor-Rung Su, De-Yuan Lu, Hao-Yi Tsai, Tin-Hao Kuo, Tzung-Hui Lee, Tai-Min Chang
  • Patent number: 11837533
    Abstract: A semiconductor package including: a first substrate including a first surface including a first region and a second region at least partially surrounding the first region, wherein the first substrate includes a first insulating layer, a first conductive pattern in the first insulating layer, a first passivation layer disposed in the first region and the second region, and a second passivation layer disposed on the first passivation layer in the second region; an interposer overlapping the first substrate and including a second insulating layer and a second conductive pattern in the second insulating layer; a first connection terminal disposed on the first passivation layer in the first region; and a second connection terminal disposed on the second passivation layer in the second region, wherein the first conductive pattern and the second conductive pattern are connected to each other through the first connection terminal and the second connection terminal.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: December 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Ho Kim, Jang Woo Lee
  • Patent number: 11832445
    Abstract: A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on each other, a cell plug passing through the stacked structure, a select plug coupled to the cell plug, and a select pattern surrounding the select plug, wherein the select pattern includes a first conductive portion and a second conductive portion covering a sidewall and a top surface of the first conductive portion, and wherein the conductive patterns, the first conductive portion, and the second conductive portion include different materials.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: November 28, 2023
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11830842
    Abstract: A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: November 28, 2023
    Assignee: NXP USA., Inc.
    Inventors: Li Li, Lakshminarayan Viswanathan, Jeffrey Kevin Jones
  • Patent number: 11817423
    Abstract: Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventor: Pooya Tadayon
  • Patent number: 11805636
    Abstract: A memory device is disclosed. The memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer, and a second portion of the second program line is formed in a third conductive layer above the second conductive layer. A width of at least one of the second portion of the first program line or the second portion of the second program line is different from a width of at least one of the first portion of the first program line or the first portion of the second program line. A method is also disclosed herein.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsin Nien, Chih-Yu Lin, Wei-Chang Zhao, Hidehiro Fujiwara
  • Patent number: 11804430
    Abstract: An electronic component includes a first insulating layer, a resistance layer including a metal thin film that is formed on the first insulating layer, the resistance layer having a first end portion, a second end portion and a central portion between the first end portion and the second end portion, a first electrode having a first contact portion and a second contact portion spaced away from the first contact portion both of which are in contact with the resistance layer at a portion of the first end portion side with respect to the central portion of the resistance layer, a notched portion formed in the first end portion of the resistance layer and between the first contact portion and the second contact portion, and a second electrode having a contact portion in contact with the resistance layer at a portion of the second end portion side with respect to the central portion of the resistance layer.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: October 31, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Bungo Tanaka
  • Patent number: 11799004
    Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: October 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heon Bok Lee, Dae Yong Kim, Wan Don Kim, Jeong Hyuk Yim, Won Keun Chung, Hyo Seok Choi, Sang Jin Hyun
  • Patent number: 11791276
    Abstract: A device comprising a first substrate comprising a first plurality of pillar interconnects; a second substrate comprising a second plurality of pillar interconnects, wherein the second plurality of pillar interconnects is coupled to the first plurality of pillar interconnects through a plurality of solder interconnects; a passive component located between the first substrate and the second substrate; and an integrated device coupled to the first substrate.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: October 17, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Aniket Patil, Hong Bok We, Joan Rey Villarba Buot
  • Patent number: 11793003
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure, a conductor layer over and in contact with the layer of dielectric material and above the S/D contact structure, and an interconnect structure over and in contact with the conductor layer.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huang-Kui Chen, Guan-Jie Shen
  • Patent number: 11784122
    Abstract: An integrated circuit device includes a conductive line including a metal layer and an insulation capping structure covering the conductive line. The first insulation capping structure includes a first insulation capping pattern that is adjacent to the metal layer in the insulation capping structure and has a first density, and a second insulation capping pattern spaced apart from the metal layer with the first insulation capping pattern therebetween and having a second density that is greater than the first density. In order to manufacture the integrated circuit device, the conductive line having a metal layer is formed on a substrate, a first insulation capping layer having the first density is formed directly on the metal layer, and a second insulation capping layer having the second density that is greater than the first density is formed on the first insulation capping layer.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: October 10, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Choonghyun Lee, Joonyong Choe, Youngju Lee
  • Patent number: 11784171
    Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: October 10, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ae-Nee Jang, Inhyo Hwang
  • Patent number: 11784151
    Abstract: Examples herein include die to metallization structure connections that eliminate the solder joint to reduce the resistance and noise on the connection. In one example, a first die is attached to a metallization layer by a plurality of copper interconnections and a second is attached to the metallization layer opposite the first die through another plurality of copper interconnections. In this example, the copper interconnects may connect the respective die to a metallization structure in the metallization layer.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: October 10, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Aniket Patil, Hong Bok We, Marcus Hsu
  • Patent number: 11776982
    Abstract: An image sensor chip includes a lower chip, an upper chip stacked on the lower chip and including a photoelectric element, a via hole penetrating through the upper chip and penetrating through at least a portion of the lower chip, and a conductive connection layer electrically connecting the lower chip and the upper chip to each other in the via hole. The upper chip includes an upper substrate, an upper isolation layer and an upper element on the upper substrate, a connection contact plug, and a multilayer interconnection line electrically connected to the connection contact plug. A distance between an upper surface of the connection contact plug and an upper surface of the upper isolation layer is greater than a distance between an upper surface of an upper gate electrode of the upper element and an upper surface of the upper isolation layer.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minho Jang, Doowon Kwon, Dongchan Kim, Bokwon Kim, Kyungrae Byun, Jungchak Ahn, Hyunyoung Yeo
  • Patent number: 11769766
    Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kam-Tou Sio, Jiann-Tyng Tzeng, Chung-Hsing Wang, Yi-Kan Cheng
  • Patent number: 11769732
    Abstract: An integrated circuit (IC) with reconstituted die interposer for improved connectivity has at least one device or component mounted on an exterior upper surface that couples to a die in an interposer layer within the package. The interposer layer may have interconnect structures, where a first interconnect structure has vias of a first pitch and a second interconnect structure has vias of a second pitch greater than the first pitch. In this manner, the interposer layer acts as a device that can allow conductive coupling for other devices with those pitches to support interconnections between those devices and other devices within the interposer layer.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: September 26, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Jonghae Kim, Aniket Patil
  • Patent number: 11749657
    Abstract: The present disclosure provides a fan-out chip packaging structure and a method to fabricate the fan-out chip package. The fan-out chip packaging structure includes a first redistribution layer, a second redistribution layer, metal connecting posts, a semiconductor chip, a first packaging layer, a stacked chip package, a passive element, a filling layer, a metal bumps, and a second packaging layer. By means of the present disclosure, various chips having different functions can be integrated into one package structure, thereby improving the integration level of the fan-out packaging structure. By means of the first redistribution layer, the second redistribution layer, and the metal connecting posts, a three-dimensional vertically stacked package is achieved.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: September 5, 2023
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Yenheng Chen, Chengchung Lin
  • Patent number: 11742403
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a first conductive member, and an insulating part region. The second electrode includes a first electrode portion. The semiconductor member includes a first semiconductor region. The first semiconductor region includes first to third partial regions. The first partial region is between the first electrode and the first electrode portion. The second partial region is between the first and third electrodes. The third partial region is between the first partial region and the first electrode portion. The third partial region includes first and second positions. The second position is between the first partial region and the first position. The first conductive member includes first and second portions. The first portion is between the second partial region and the third electrode. The insulating part region includes first and second insulating regions.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: August 29, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Inokuchi, Hiro Gangi, Yusuke Kobayashi, Hiroki Nemoto
  • Patent number: 11742266
    Abstract: A method comprises removing a portion of molding compound from a side of a package structure by a laser ablation process to create an opening that exposes a portion of a conductive clip, depositing solder paste on the exposed portion of the conductive clip, and reflowing the solder paste. The laser ablation process in one example is a pulsed laser ablation process that includes raster scanning a laser along a portion of the side of the package structure to create the opening. Depositing the solder paste in one example includes performing a dispense process or a screening process that deposits solder paste in the opening onto the exposed portion of the conductive clip.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 29, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Laura May Antoinette Dela Paz Clemente, James Raymond Maliclic Baello