Patents Examined by Fernando L. Toledo
  • Patent number: 10879302
    Abstract: An image sensor may include a photoelectric device configured to selectively absorb light associated with a first color of three primary colors, a semiconductor substrate that is stacked with the photoelectric device and includes first and second photo-sensing devices configured to sense light associated with second and third colors of three primary colors. The first and second photo-sensing devices may have different thicknesses, different depths from a surface of the semiconductor substrate, or different thicknesses and different depths from the surface of the semiconductor substrate. At least one part of a thickness area of the first photo-sensing device may overlap at least one part of a thickness area of the second photo-sensing device in a parallel direction extending substantially parallel to the surface of the semiconductor substrate.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Hee Lee, Gae Hwang Lee, Sung Young Yun, Dong-Seok Leem, Yong Wan Jin
  • Patent number: 10879371
    Abstract: Embodiments described in this disclosure relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In some examples, after an interfacial layer and a gate dielectric layer are deposited, a rapid anneal process, such as laser anneal or flash lamp anneal process, is performed in a controlled ambient nitrogen-containing environment to form a nitrided portion in the gate dielectric layer. The nitrided portion passivates the defects at the surface of the gate dielectric layer and can serve as a barrier to prevent etchant chemistry and defects/dopants from the subsequent gate stack layers from affecting or diffusing through the gate dielectric layer. Particularly, the rapid anneal process is performed on a millisecond scale to confine nitrogen atoms in the gate dielectric layer without diffusing into the underlying interfacial dielectric and/or any neighboring structure such as fin.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Yun Li, Huicheng Chang, Che-Hao Chang, Hung-Yao Chen, Cheng-Po Chau, Xiong-Fei Yu, Terry Huang
  • Patent number: 10879446
    Abstract: Embodiments of the present disclosure relate to quantum circuit assemblies implementing superconducting qubits, e.g., transmons, in which SQUID loops and portions of FBLs configured to magnetically couple to the SQUID loops extend substantially vertically. In contrast to conventional implementations, for a vertical SQUID according to various embodiments of the present disclosure, a line that is perpendicular to the SQUID loop is parallel to the qubit substrate. A corresponding FBL is also provided in a vertical arrangement, in order to achieve efficient magnetic coupling to the vertical SQUID loop, by ensuring that at least a portion of the FBL designed to conduct current responsible for generating magnetic field for tuning qubit frequency is substantially perpendicular to the substrate.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Roman Caudillo, Lester Lampert, David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, James S. Clarke
  • Patent number: 10879468
    Abstract: To provide a layer such as a charge transport layer having a refractive index significantly lowered without impairing electrical conductivity and surface roughness, and a method for producing it. A deposited film composition obtained by co-depositing a fluorinated polymer having a saturated vapor pressure at 300° C. of at least 0.001 Pa and an organic semiconductor material.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: December 29, 2020
    Assignees: National University Corporation Yamagata University, AGC Inc.
    Inventors: Daisuke Yokoyama, Takefumi Abe, Yasuhiro Kuwana
  • Patent number: 10872953
    Abstract: Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming a counter doped semiconductor layer on a physically exposed and recessed surface of a semiconductor substrate after formation of a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on a portion of the semiconductor substrate. The presence of the counter doped semiconductor layer isolates the source/drain regions from the semiconductor substrate and eliminates parasitic transistor formation.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: December 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari
  • Patent number: 10872866
    Abstract: A semiconductor package including a substrate having a surface, and a conductive element on the first surface and electrically coupled to the substrate. The conductive element has a principal axis forming an angle less than 90 degrees with the surface.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 22, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Jenchun Chen
  • Patent number: 10871415
    Abstract: Systems and methods are disclosed for packaging sensors for use in high temperature environments. In one example implementation, a sensor device includes a header; one or more feedthrough pins extending through the header; and a sensor chip disposed on a support portion of the header. The sensor chip includes one or more contact pads. The sensor device further includes one or more wire bonded interconnections in electrical communication with the respective one or more contact pads and the respective one or more feedthrough pins. The sensor device includes a first sealed enclosure formed by at least a portion of the header. The first sealed enclosure is configured for enclosing and protecting at last the one or more wire bonded interconnections and the one or more contact pads from an external environment.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 22, 2020
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Alexander A. Ned, Leo Geras, Sorin Stefanescu
  • Patent number: 10868152
    Abstract: A semiconductor device including a memory cell, the semiconductor device including: a floating gate provided at a semiconductor substrate with a first insulation film inbetween, and including a pointed portion having a pointed end at one end side; a spacer provided at the floating gate; a second insulation film provided between the floating gate and the spacer and that covers a side surface of the spacer at the one end side; and a control gate that contacts a side surface of the floating gate at the one end side via a third insulation film and that contacts the side surface of the spacer at the one end side via the second insulation film and the third insulation film.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 15, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Akira Chiba
  • Patent number: 10868061
    Abstract: According to an aspect, a sensor packaging structure includes a sensor die having a first surface and a second surface opposite the first surface, where the sensor die defines a sensor edge disposed between the first surface and the second surface. The sensor packaging structure includes a bonding material having a first surface and a second surface opposite the second surface, where the bonding material defines a bonding material edge disposed between the first surface of the bonding material and the second surface of the bonding material. The sensor packaging structure includes a transparent material, where the bonding material couples the sensor die to the transparent material. The sealing material is disposed on an interface between the sensor die and the bonding material, and at least one of a portion of the sensor edge or a portion of the bonding material edge.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 15, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Weng-Jin Wu
  • Patent number: 10868181
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Mu Li, Wei-Yang Lee, Wen-Chu Hsiao
  • Patent number: 10868131
    Abstract: A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Hao Yeh, Ching Yu Huang
  • Patent number: 10861990
    Abstract: A method of manufacturing an epitaxial silicon wafer that includes growing a silicon single crystal ingot doped with a boron concentration of 2.7×1017 atoms/cm3 or more and 1.3×1019 atoms/cm3 or less by the CZ method; producing a silicon substrate by processing the silicon single crystal ingot; and forming an epitaxial layer on a surface of the silicon substrate. During growing of the silicon single crystal ingot, the pull-up conditions of the silicon single crystal ingot are controlled so that the boron concentration Y (atoms/cm3) and an initial oxygen concentration X (×1017 atoms/cm3) satisfy the expression X??4.3×10?19Y+16.3.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: December 8, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Kazuhisa Torigoe, Toshiaki Ono
  • Patent number: 10862008
    Abstract: A ceramic conversion element, a light-emitting device and a method for producing a ceramic conversion element are disclosed. In an embodiment a ceramic conversion element includes a central region with a structured top surface including a plurality of structure elements and a frame surrounding the central region, the frame having a planar top surface, wherein the central region and the frame are formed as one piece, and wherein the ceramic conversion element is configured to convert primary radiation into secondary radiation of a different wavelength range.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: December 8, 2020
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Darshan Kundaliya, Norwin von Malm, Jeffery J. Serre
  • Patent number: 10854278
    Abstract: A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10854529
    Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin
  • Patent number: 10854609
    Abstract: Wells formed in a semiconductor device can be discharged faster in a transition from a stand-by state to an active state. The semiconductor device includes an n-type well applied, in an active state, with a power supply voltage and, in a stand-by state, with a voltage higher than the power supply voltage, a p-type well applied, in the active state, with a ground voltage and, in the stand-by state, with a voltage lower than the ground voltage, and a path which, in a transition from the stand-by state to the active state, electrically couples the n-type well and the p-type well.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: December 1, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Akira Tanabe
  • Patent number: 10854744
    Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: December 1, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Yoshihiro Matsushima, Shigetoshi Sota, Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Ryou Kato
  • Patent number: 10847674
    Abstract: A light emitting device includes: a substrate; a first electrode and a second electrode provided at a distance from each other on the substrate and extending in one direction; a plurality of light emitting diodes provided between the first electrode and the second electrode, and connected to the first electrode and the second electrode; and a residual pattern provided between at least one of the plurality of light emitting diodes and the substrate.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 24, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yeoung Keol Woo, Chul Min Bae
  • Patent number: 10840347
    Abstract: Provided is a semiconductor device with negative differential transconductance. The semiconductor device includes a substrate, a gate electrode formed on the substrate, an insulating layer formed on the gate electrode, a source electrode material layer formed on the insulating layer, a semiconductor material layer formed on the insulating layer to be hetero-joined to the source electrode material layer, a source electrode formed on the source electrode material layer, and a drain electrode formed on the semiconductor material layer. A work function of the source electrode material layer is controlled by a gate voltage applied through the gate electrode, and the source electrode material layer shows negative differential transconductance depending on a level of the gate voltage.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: November 17, 2020
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Jaewoo Shim, Dong Ho Kang
  • Patent number: 10840139
    Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a field insulating layer on the substrate, the field insulating layer wrapping a side wall of the fin type pattern, a gate electrode on the fin type pattern, the gate electrode extending in a second direction intersecting with the first direction, a first spacer on a side wall of a lower part of the gate electrode, and an etching stop layer extending along a side wall and an upper surface of an upper part of the gate electrode, along a side wall of the first spacer, and along an upper surface of the field insulating layer.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Geum Jung Seong, Seung Soo Hong, Young Mook Oh, Jeong Yun Lee