Abstract: Reactive ion etch (RIE) selectivity during etching of a feature nearby embedded structure is improved by using a silicon oxynitride layer formed with carbonization throughout layer.

Abstract: The invention is directed to piezoelectric device having a vibration space that achieves a high degree of airtightness which is not readily reduced, and a manufacturing method thereof. First and second hollow layers are formed at first and second surfaces of a piezoelectric substrate to form first and second cavities around first and second electrodes respectively. The first and second cavities each have a uniform width and extend between a first surface and an opposing second surface of the first and second hollow layers respectively, around vibration portions of the piezoelectric element. First and second sealing layers are each formed on the second surface of the first and second hollow layers to seal the first and second cavities.

Abstract: Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined on a sacrificial substrate. The openings may be within the surface of the substrate, or in one or more layers deposited on the surface of the sacrificial substrate. Each spring contact element has a base end portion, a contact end portion, and a central body portion. The contact end portion is offset in the z-axis (at a different height) than the central body portion. The base end portion is preferably offset in an opposite direction along the z-axis from the central body portion. In this manner, a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the sacrificial substrate.

Abstract: The semiconductor device of the present invention includes: a substrate; a first conductor film supported by the substrate; an insulating film formed on the substrate to cover the first conductor film, an opening being formed in the insulating film; and a second conductor film, which is formed within the opening of the insulating film and is in electrical contact with the first conductor film. The second conductor film includes: a silicon-containing titanium nitride layer formed within the opening of the insulating film; and a metal layer formed over the silicon-containing titanium nitride layer. The metal layer is mainly composed of copper.

Abstract: A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized during an open/short checkup of a semiconductor device. The semiconductor device includes a semiconductor substrate having a plurality of device isolation regions, first and second n-wells horizontally spaced from either of the plurality of device isolation regions, a p-channel transistor formed in the second n-well, an input protection transistor horizontally spaced from the first n-well and the device isolation region, on a symmetrical portion by the first n-well to the second n-well, and a guard ring formed between the first n-well and the input protection transistor.

Abstract: A method to form a silicon on insulator (SOI) device using wafer bonding. A first substrate is provided having an insulating layer over a first side. A second substrate is provided having first isolation regions (e.g., STI) that fill first trenches in the second substrate. Next, we bond the first and second substrate together by bonding the insulating layer to the first isolation regions and the second substrate. Then, a stop layer is formed over the second side of the second substrate. The stop layer and the second side of the second substrate are patterned to form second trenches in the second substrate. The second trenches have sidewalls at least partially defined by the isolation regions and the second trenches expose the second insulating layer. The second trenches define first active regions over the first isolation regions (STI) and define second active regions over the insulating layer. Next, the second trenches are filled with an insulator material to from second isolation regions.

Abstract: A light emitting device includes an LED chip fixed to an electrode body via a conductive layer of In or an In alloy. The conductive layer is in ohmic-contact with an n-type ZnSe crystal substrate of the LED chip. To make the device, In or an In alloy is melted on the electrode body, the ZnSe substrate is placed directly on the melted In or In alloy and then subjected to at least one of vibration and pressure to achieve a good bond and ohmic contact between the In or In alloy and the ZnSe substrate.

Abstract: A method for eliminating copper atomic residue from the channel oxide layer on semiconductors after chemical-mechanical polishing is provided. After chemical-mechanical polishing, the silicon oxide is plasma etched to remove its surface and any residue. After plasma etching, an etch stop layer of silicon nitride is deposited by chemical-vapor deposition. Both the plasma etch of the silicon dioxide and the chemical-vapor deposition of the silicon nitride can be performed in the same vacuum chamber in the same semiconductor processing tool with only a change of the gas mixture.

Abstract: A semiconductor memory device and a fabricating method thereof are provided. In the course of forming a buried contact hole after forming a bit line pattern, the buried contact hole is formed by a self aligned contact process using capping layers included in the bit line pattern, thereby securing an overlap margin. Formation of a deep inner cylinder type capacitor unit prevents a bridge defect between lower electrodes of the capacitor and suppresses the occurrence of particles while simplifying the fabrication process. Furthermore, a mechanism for forming a second metal contact hole can simplifies the problems related to etching and filling of the second metal contact hole.

Abstract: Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.

Abstract: An electronic power device is integrated on a substrate of semiconductor material having a first conductivity type, on which an epitaxial layer of the same type of conductivity is grown. The power device comprises a power stage PT and a control stage CT, this latter enclosed in an isolated region having a second type of conductivity type. The power stage PT comprises a first buried area having the second type of conductivity type and a second buried area, partially overlapping the first buried area and having the first conductivity type. The isolation region and the control stage CT comprise respectively a third buried area, having the second conductivity type, and a fourth buried area, partially overlapped to the third buried area and having the first conductivity type. Said first, second, third and fourth buried areas are formed in the epitaxial layers at a depth sufficient to allow the power stage PT and the control stage CT to be entirely formed in the epitaxial layers.

Abstract: A solid imaging device including: a semiconductor substrate of a first conductivity types a layer of a second conductivity type formed on a surface of the semiconductor substrate, the layer at least including a photosensitive portion of the second conductivity type; and a MOS transistor of the second conductivity type coupled to the photosensitive portion, wherein the solid imaging device further includes a layer of the first conductivity type in at least a channel region of the MOS transistor of the second conductivity type, the layer of the first conductivity type having an impurity concentration which is higher than an impurity concentration of the semiconductor substrate, and wherein at least a portion of a boundary of the layer of the second conductivity type is in direct contact with the semiconductor substrate.

Abstract: The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.

Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.

Abstract: For fabricating a field effect transistor on a semiconductor substrate, a gate dielectric of the field effect transistor is formed on a semiconductor substrate. A doped gate electrode, which may be comprised of silicon germanium (SiGe) for example, is formed on the gate dielectric. An amorphous semiconductor structure, which may be comprised of amorphous silicon for example, is formed on the doped gate electrode. A hardmask structure comprised of a hardmask dielectric material is formed on the amorphous semiconductor structure. The gate dielectric, the doped gate electrode, the amorphous semiconductor structure, and the hardmask structure form a gate stack. Liner dielectric structures are formed on sidewalls of the gate stack. A dopant is implanted into exposed regions of the semiconductor substrate after forming the liner dielectric structures on the sidewalls of the gate stack.

Abstract: A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.

Abstract: Provided is a semiconductor device with a silicide protection structure that prevents the over-etching of a source/drain layer in forming a contact hole and prevents a voltage drop in surge voltage without increasing the area of the source/drain layer, as well as a manufacturing method of the device. There is defined an active region (AR) of an MOS transistor and a gate electrode (10) that constitutes a field-shield isolation structure formed in a rectangular loop shape. Over the FS gate electrode (10) and the active region (AR), a gate electrode (20) of the MOS transistor is formed so as to divide the FS gate electrode (10) in two. Each of the active regions (AR) facing each other across the gate electrode (20) has a silicide protection structure (PS1), whose surrounding is an S/D layer (30), and a silicide film (SF1) is formed over the structure (PS1).

Abstract: A method of fabricating integrated circuit wafers, in accordance with this invention comprises the following steps. Provide an integrated circuit wafer having devices formed therein covered with a metal layer and a photoresist layer over the metal layer which is selectively exposed and developed forming a photoresist mask. Introduce the wafer into a multi-chamber system, patterning the metal layer by etching and then exposing the mask to light in a cooled chamber wherein the light is derived from a source selected from a mercury lamp and a laser filtered to remove red and infrared light therefrom before exposure of the wafer thereto. The chamber is cooled by a refrigerant selected from water and liquefied gas. Then remove the wafer, and load it into a photoresist stripping tank to remove the photoresist mask with a wet photoresist stripper. Place the wafer in a batch type plasma chamber after removing the photoresist mask.

Abstract: For fabricating a vertical field effect transistor on a semiconductor substrate, a first layer of dielectric material is deposited on the semiconductor substrate. A layer of metal is then deposited on the first layer of dielectric material, and a second layer of dielectric material is deposited on the layer of metal. A channel opening is etched through the second layer of dielectric material, the layer of metal, and the first layer of dielectric material. A source and drain dopant is implanted through the channel opening and into the semiconductor substrate to form a drain region of the vertical field effect transistor in the semiconductor substrate. Metal oxide is then formed at any exposed surface of the layer of metal on sidewalls of the channel opening in a thermal oxidation process to form a gate dielectric of the vertical field effect transistor.

Abstract: In one embodiment, a protective layer is formed on the top surface of the gate electrode of a transistor device prior to the formation of low resistance metal silicide regions on the drain and source regions. The protective layer prevents the simultaneous formation of a metal silicide region on the gate electrode. Thereafter, a process layer is formed above the source/drain regions and the cover layer that is positioned above the gate electrode. Next, a surface of the process layer is planarized to expose the cover layer, and the cover layer is removed. Then, a metal silicide region is formed above the gate electrode by depositing a layer of refractory metal and performing at least one anneal process.