Abstract: A real-time distributed data-base system that stores in the local memory of each processor copies of only those variables necessary for execution of the programs in that processor. Performance is enhanced by using the absolute address of variables in each program reference, with automatic updating of all program references when the location of variables are changed. Flexibility in user application programming is enhanced by permitting combination and conditional updates of variables through the interaction of multiple processors.

Abstract: A uniprocessor if formed on plural independently controlled chips each including a primary instruction driven controller and a secondary error driven self-sequencing controller. Each instruction is supplied in parallel to each primary controller which generates an EXIT signal, as it completes execution, to a common external EXIT line. Hardware monitors the local EXIT signal and the common EXIT line state and activates the secondary controller, when a mismatch is detected, to set an on-chip reset predominant error latch driving a common external ERROR line, an ERROR-state on which also sets the latches and activates any inactive secondary controller to drive its chip to a first predetermined state and to reset its latch. When no ERROR signal remains, the secondary controllers cycle in synchronism through an ERROR routine, exiting to instruction control.

Abstract: A multiprocessor computer system having n parallel-operating computer modules which each include a processor module, a memory module and a data word reconstruction module, wherein each module of said system processes the same piece of data simultaneously and in parallel. The data words are applied to a reducing encoder so that code symbols stored in the relevant computer modules form a code word. The relevant error-correction code has a simultaneous correction capability in at least two code symbols. Each data word reconstruction module receives the entire code word in order to reconstruct the data word therefrom. Each computer module also has an input/output memory module. This module receives a coded data word which is decoded when it is presented again. Decoding is performed so that each bit in the input/output memory is mapped on at the most one bit of the associated memory module.

Abstract: A computer keyboard matrix overlay panel carries indicia indicating the functions of keys and other operating instructions, to replace a significant part of the information formerly set forth in an external instruction manual. Individual panels are coded by incorporated switch parts acting with cooperating computer switch parts to set up a particular operating mode for which the respective key functions are identified when the panel is in place over the computer keyboard keys, the functions being selected by the use of two sequential, non-simultaneous keystrokes involving any of the keys on the keyboard. The panels also serve as software media by incorporation of data strips along panel edges to permit carrying program and data information external to the computer memory which is readable into the computer by corresponding transducers. The panel codes can change the comptuer mode and enter corresponding programs, subroutines, constants, and variable data.

Abstract: A memory system which comprises a mainstore for storing lines of data and a buffer store for storing lines of data that are a subset of the data stored in the main store. The buffer store is comprised of a plurality of associativities. A line of data stored in the buffer having a given address may be stored in any one of the plurality of associativities. A tag store stores a tag for the associativities. A field from a buffer store address is compared with the stored tag in the tag store to produce a data selection signal for selecting from among the plurality of associativities the proper line of data. When the buffer has only two associativities, a bit in the buffer store address which has different values for the two associativities is tested, and thus the proper line of data is selected. The bit position is indicated by a pointer stored in the tag array. A selection of one of two data lines is made prior to a determination of the presence or validity of data in the buffer store.

Abstract: A system and method are disclosed for automatically refreshing a dynamic random access memory (DRAM) under a plurality of different operational conditions of an associated processor. When the processor is normally executing instructions it generates active signals which enable a generator circuit to generate timing signals. A hidden refresh circuit uses status signals and a first part of these timing signals to generate a refresh pulse during an opcode fetch cycle of each instruction being executed by the processor. A control circuit uses each refresh pulse and a second part of the timing signals to generate a row refresh signal to refresh a row in the DRAM indicated by a row address from a counter and a row address clock to increment the counter to the next row to be refreshed by the following row refresh signal.

Abstract: An interface apparatus for interconnecting signal lines of a computer connector and a peripheral device connector with non-matching interconnect patterns having mismatched data lines or open inputs on handshake or control lines. A pair of conductive paths extend between the connectors, with each path interconnecting one data line of the computer connector with one data line of the peripheral connector. Lights indicate mismatched interconnection of the data lines, and a switch selectively reverses the interconnection of the data lines. Additional conductive paths extend between the connectors, each path interconnecting at least one handshake or control line of each connector with at least one handshake or control line of the other connector. Two pairs of interconnecting handshake lines are each provided with a switch in gang with the data line switch for selectively reversing their electrical interconnection.

Abstract: Synchronization of peripheral operation with that of a processor in a multi-microprocessor implemented data processing system is achieved by bus cycle alteration. A logic circuit is provided for monitoring the condition of a peripheral's status bits and for preventing an appropriate processor control signal from completing the present bus cycle if the peripheral of interest is not able to accept an access. The peripheral of interest is readily identified by providing unique memory mapped locations, one for each system peripheral, that are responsively connected to the logic circuit.

Abstract: A memory refresh circuit controls the refreshing of dynamic RAM included in a system wherein a control store outputs micro-code instructions to control the system operation in response to sequences specified by a sequence and interrupt logic circuit (SIL). A counter transmits certain counts of system machine cycles to an array logic device. In response to one count, the array logic device generates a memory refresh request signal which is applied to a RAM address logic circuit (RAL). The RAL monitors the micro-code instruction output at each machine cycle to determine whether the instruction will access the dynamic RAM during that machine cycle, and if no memory access is detected, the RAL generates a signal to initiate a memory refresh operation, which operation requires two machine cycles to complete.The array logic device also monitors the micro-code instructions to determine if and when a refresh operation was initiated.

Abstract: A digital computer memory prefetches, or reads ahead, a next sequential, odd, address data word from a backing memory store containing all such odd address data words to a high speed buffer register simultaneously that the memory fetches the immediately preceding, even address data word from a backing memory store containing all such even address data words to that requestor-user, one of selective one(s) of a multiplicity of such requestor-users with which the memory communicates, which is addressably reading such even address data word. Selective one(s) of the requestor-users, which one(s) is (are) predominantly sequential in successive read addressings, does (do) enable such prefetching through a unique signal communicated to the memory. Remaining requestor-users do disable, via the alternative condition of the same signal, any prefetching; causing thereby no disturbance to the priorly read-ahead, odd address, data word.

Abstract: An addressing and control system for a mass memory which is partitioned into selectable pages of individually specified size. The invention generates a composite address for the mass memory so that a microcomputer of limited address size can access the mass memory by individually specified page. One circuit implementation utilizes a register to latch page size and selection information for subsequent combination with address information to generate a full address for the mass memory. In that situation, the size register multiplexes the address bus information and page selection information to maintain correspondence between the specified size of the page and the total addressing bits available. In another form, the invention provides for supplementing the number of address bus bits with bits transmitted over the data bus to extend the bit length of the address used to access the mass memory.

Abstract: A key-accessed (indexed) file is organized such that the file structure consists only of two levels, an index level and a data level. Both levels are permanently stored on a page-organized secondary storage medium that supports random accessing of the pages. The index level is designed to have a fixed and specifiable number of pages and is stored entirely in the computer's memory when the file is in use. The fixed size of the index is made possible by having each index entry reference a data node with a growing (or shrinking) number of data pages as the file changes in size. Avoiding the accessing of more than one of the data pages referenced by an index entry is accomplished by means of an address computation that utilizes bits of the search argument.

Abstract: A multi-stage modem status register, which has at least one stage which is ordinarily unused, is employed to receive operating condition signals from an associated modem. In addition bistable circuitry, which exists as part of the control circuitry of a transceiver, is used: (1) to provide a first binary signal when a data processor (with which the present system is used), generates a "resynchronization request" signal; and (2) to provide a second binary signal in response to resynchronization being achieved. The bistable circuitry is connected to the above described ordinarily unused stage to enable one or the other of the binary signals to be present. The multi-stage modem status register is regularly interrogated and the results are sent to both a memory and a comparison device. Output signals from the memory are transmitted to said comparison device, at the time that the results of a subsequent interrogation are transmitted to the comparison device.

Abstract: A data transfer system for transferring data from magnetic tape peripheral units to a peripheral-controller for temporary storage and subsequent transfer to a host computer. A tape control unit, connected to the magnetic tape peripheral units, provides clock signals to a synchronization logic circuit which controls the transfer of data through two sequential latching registers to a buffer memory in the peripheral-controller. The two sequential latching registers function as a buffering delay element together with an automatic read logic unit which allows the read logic unit to use a lesser number of cycle-steal times than would ordinarily be required, while still controlling a steady uninterrupted flow of data words.

Abstract: A computer virtual memory system having a translation lookaside buffer (TLB) in which the result of a dynamic address translation system is stored when in a normal mode or when a non-privileged instruction is executed, but the result is not stored when in a privileged mode or when a privileged instruction is executed, such as a storage key operation. The storage does not occur even though the effective address of the privileged instruction is translated into a physical address.

Abstract: Method and apparatus for allowing multiple enclosures (10) to be connected so that their respective motherboards (15) together define a single bus. System-wide arbitration is carried out asynchronously on an enclosure basis while arbitration within each enclosure occurs synchronously. A bus repeater (20, 25, 25') is provided at each of the upstream and downstream ends of each enclosure's motherboard. The upstream bus repeater (20) in a given enclosure is coupled by a flexible connector cable (30) to the downstream bus repeater (25, 25') in the enclosure immediately upstream. One of the bus repeaters (say the upstream one) has the status as master or arbiter while the other has the status of a slave. The connector cables have two sets of lines (32, 35), thereby allowing the bus repeaters to pass two basic types of signals: (a) bused signals (address, data) which are made available to the relevant unit boards; and (b) private signals which are passed only to the bus repeaters.

Abstract: An operation mode setting system is provided in a microprocessor operable in a plurality of operation modes. The operation mode setting system has a signal input line through which an analog voltage corresponding to any of the respective operation modes is applied to an analog-to-digital converter circuit which is built in the microprocessor. The output signal from the analog-to-digital converter circuit is decoded by a decoder, and the microprocessor is set at the predetermined operation mode in response to the decoded output signal.

Abstract: A system for the management of the physical memory of a processor which utilizes a base register which is loaded, for each virtual address of the memory, by a base address of a discriptive register corresponding to a task to be performed by the processor. This system utilizes a descriptive register table, an adder receiving the binary value of the base address of the first descriptive register, and the binary value of the index corresponding to the first register. The outputs of the adder address one of the inputs of the descriptive register table, thus selecting a segment descriptive register corresponding to the task to be performed. Each of the descriptive registers of the table contains control bits sent to the processor which makes it possible for the processor to check whether, for the segment to which the processor must have access, the processor must operate in the local or overall mode and whether the processor must process an input-output operation or an access to the memory.

Abstract: A memory system has a first memory such as a magnetic bubble memory and a second memory such as a RAM having a faster access time than the first memory. The first memory is divided into a plurality of blocks each of which has program steps stored therein. The second memory has a plurality of unit chains which correspond to the blocks of the first memory respectively and in each of which step information representative of the number of steps stored in the corresponding block and pointer information indicative of a connection to a next block are stored. The step information in the unit chains are successively read in accordance with predetermined start block information and the pointer information to count the total number of steps on the basis of the read step information. From the first memory is read information in the block corresponding to the unit chain of the second memory with respect to which the counting is made when the counted number of steps reaches or exceeds a program step number to be detected.

Abstract: A data processing system having a performance measurement system which is capable of setting desired performance measurement items. In the performance measuring system an interrupt by internal timer is used for triggering performance measurement, the performance measurement system executes the processings after this timer interrupt, and processing results for each measurement item are collected in the main storage.