Abstract: A method for fabricating a photodetector device including a single pixel or an array of pixels, each of which is constituted by a single vertical type SIT (Static Induction Transistor). First and second main electrode regions are formed on respective first and second main surfaces of a silicon wafer. Control gate and shielding gate regions, as well as drain and source regions as well, are formed using a single common masking step. As a result, the formation of these regions is precisely controlled, resulting in superior photoresponse characteristics.

Abstract: A method for forming a semiconductor photodetector array having a matrix of pixels, each constituted by a single SIT (Static Induction Transistor). A field oxide layer is formed on a first main surface of a silicon wafer. Portions of a field oxide layer are then removed from predetermined regions of the first main surface. In these predetermined regions are formed a control gate region and a shielding gate region, with the shielding gate region surrounding the control gate region. Oxide layers are formed on the control gate region and shielding gate region. Portions of the field oxide layer between the control gate region and shielding region are removed to partially expose the first main surface of the silicon wafer, and a first main electrode region is formed in the exposed portion. A first conductive electrode is then deposited on the first main region, whereupon the entirety of the first main surface of the silicon wafer is covered with a first insulating layer.

Abstract: Liquid phase epitaxy (LPE) growth of a Group III-V semiconductor compound layer upon a Group III-V semiconductor compound substrate containing phosphorus is accomplished in a graphite meltholder by heating the substrate in an atmosphere of nitrogen or helium and contacting the substrate with a liquid melt, capable of growing the layer, in an atmosphere of hydrogen.

Abstract: Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process of this invention involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.

Abstract: Josephson junction integrated circuits of the current injection type and magnetically controlled type utilize a superconductive layer that forms both Josephson junction electrode for the Josephson junction devices on the integrated circuit as well as a ground plane for the integrated circuit. Large area Josephson junctions are utilized for effecting contact to lower superconductive layers and islands are formed in superconductive layers to provide isolation between the groundplane function and the Josephson junction electrode function as well as to effect crossovers. A superconductor-barrier-superconductor trilayer patterned by local anodization is also utilized with additional layers formed thereover. Methods of manufacturing the embodiments of the invention are disclosed.

Abstract: A body of silicon has sectors of N-type and P-type covered by silicon oxide gate layers with adjacent regions covered by a thicker silicon oxide field layer. Gate members of N-type polycrystalline silicon are placed on the gate layers to define an N-type channel region in the N-type sector and a P-type channel region is the P-type sector. P-type conductivity imparting material is introduced into the remaining regions of the N-type sector to convert them to P-type source/drain regions with an intervening N-type channel region, and N-type conductivity imparting material is introduced into the remaining regions of the P-type sector to convert them to N-type source/drain regions with an intervening P-type channel region. The exposed silicon oxide is grown to a thicker field layer and a protective oxide is formed on the polycrystalline gate members.

Abstract: During liquid phase epitaxial growth of a compound semiconductor layer on a substrate, an unsaturated solution is brought into contact with a solute source crystalline plate. The plate dissolves into the solution, which creates a supercooling condition in the solution without a decrease in the temperature of the solution. The crystalline plate has a denser crystal face than that of the substrate, and/or the lattice constant of the crystalline plate is considerably different from that of the substrate.

Abstract: In the manufacture of an InP/(In,Ga) (As,P) buried rib laser, the sides of the laser are profiled to have surfaces extending in {111} A planes down to the junction between the active and lower confining layers, and to have surfaces extending in other planes beneath this junction. In the subsequent epitaxial regrowth nucleation above this junction between the surfaces is discriminated against in favor of growth beneath this junction so that the regrowth up the sides of the rib is automatically temporarily arrested in the vicinity of this junction.

Abstract: A method for manufacturing a semiconductor integrated circuit which comprises providing a semiconductor substrate, forming a recess in the substrate through a pattern of an oxidation-inhibiting film, forming a thin film of a material capable of being oxidizing into an insulating oxide such as silicon on the side and/or bottom surface of the recess, and oxidizing the thin film to fill up with the recess with the resulting oxide which increases in volume.

Abstract: Semiconductor devices are made by a process in which impurity is introduced, by ion implant, for example, after electrode layers are in place so that inaccuracies in alignment of masks or patterns are compensated. The implanted impurity changes the electrical characteristics of portions of the semiconductor device affected by the registration inaccuracies whereby malfunctions in the completed devices are prevented.

Abstract: A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PN junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

Abstract: Schottky-barrier MOS and CMOS devices are significantly improved by selectively doping the regions surrounding the Schottky-barrier source and drain contacts. For p-channel devices, acceptor doping is carried out in either a one-step or a two-step ion implantation procedure. For n-channel devices, donor doping is carried out in a two-step procedure. In each case, current injection into the channel is enhanced and leakage to the substrate is reduced while still maintaining substantial immunity to parasitic bipolar transistor action (MOS devices) and to latchup (CMOS devices).

Abstract: An improved MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a self-aligned gate process which consists of an implanted channel stopper underneath a thick field oxide, depletion and enhancement mode device channel implants, implanted source and drain regions, selective oxidation to form self-aligned gates, metal-semiconductor junctions as control elements, barrier metal and a thin film metallization system. The process and device structure are suited for high packing density, very low speed power product and ease of fabrication making it attractive for digital applications.

Abstract: A method of forming a high sensitivity, large area, negative electron affty (NEA), infrared sensitive transmission mode, GaAs on AlGaAs photocathode structure with the GaAs layer being of controlled homogeneous thickness and having a blemish-free surface. The structure is formed by using a combination of liquid and vapor phase epitaxial techniques, i.e., hybrid epitaxy.

Abstract: A gate-source structure and fabrication method for a static induction transistor having improved gain and frequency characteristics and having relatively simple fabrication requirements. The method and the device are embodied by gate regions diffused into the bottom of parallel recessed grooves located in a high resistivity epitaxial semiconductor layer, the surface of the semiconductor layer having a previously diffused source region located between the recessed grooves. The walls of the recessed grooves are covered with silicon dioxide.

Abstract: A method of fabricating CMOS integrated circuits including the ordered steps of: depositing a layer of phosphorus doped silicon oxide; heating the oxide layer at a temperature and duration sufficient to reflow and densify it; forming contact apertures in the oxide layer for exposing source and drain regions of transistors; and cleaning the wafer in an etchant solution for rounding off sharp edges on the oxide layer prior to contact metallization. In a preferred embodiment, all steps between forming contact apertures and through metallization are formed at a temperature that is lower than the temperature that will cause flow of the oxide layer.

Abstract: This invention provides a semiconductor device, which has a high impurity concentration diffusion region such as a drain diffusion region and a resistor comprising a polycrystalline silicon layer (which may be a load of a driver MOS transistor), and in which part of the resistor is in direct contact with the high impurity concentration diffusion region. This invention also provides a method of manufacturing a semiconductor device, which comprises the steps of forming a gate electrode and drain and source diffusion regions along the principal surface of a semiconductor substrate, then forming a polycrystalline silicon resistor layer of a comparatively low impurity concentration such that it is in direct contact with a diffusion region, and subsequently causing impurity diffusion from the diffusion region through thermal treatment to obtain ohmic contact between the diffusion region and resistor layer.

Abstract: There is herein described a process for fabricating GaAs FETs with an ion implanted channel layer wherein an ion implanted substrate is capless annealed under an arsine overpressure, and a relatively shallow portion of the outer surface of the substrate in the active layer is removed for the deposition of a gate metallic electrode.

Abstract: A process for forming zener diodes from an IC structure having coextensive layers of gate silicon dioxide and polycrystalline silicon on a substrate and self-aligned with a diffused region in the substrate. A differential oxidation of the polycrystalline silicon and substrate silicon is followed in turn by a silicon dioxide etch to expose only the polycrystalline silicon layer. Thereafter, the exposed polycrystalline silicon is etched with an etchant that does not materially etch silicon dioxide. The exposed substrate is then subjected to an ion implantation, performed with an energy sufficient to locate the peak impurity concentration below the substrate surface, and a dose sufficient to moderately dope the area originally under the polycrystalline silicon electrode while reducing the effective concentration of the opposite impurity type dopant in the diffused region of the substrate.

Abstract: A Schottky gate FET is fabricated by forming on a semiconductor substrate first and second stacks facing each other. Each stack is constructed by an ohmic electrode and a spacer film. On the substrate having stacks formed thereon an insulation layer is formed and is anisotropically etched in the direction of its thickness until the planar surface portions are exposed. As a result, portions of the insulation layer remain on opposing side walls of the stacks. After removing the spacer films to define stepped portions between each remaining portion and each electrode, a layer of a metallic material capable of forming a Schottky barrier with the substrate is formed. The remaining portions are removed to pattern the metallic material layer, thereby forming a Shottky gate electrode.