Abstract: The invention provides a unique sub-micron dimensioned NPN type transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Slots made in the substrate permit angle evaporation of etch-resist to protect the active region while it is disconnected from the substrate by etching therebeneath via the slots.

Abstract: The invention is a transistor or array thereof and method for producing same in sub-micron dimensions on a silicon substrate doped P or N type by forming slots in spaced apart relation across the substrate to define semi-arrays of V shaped intermediate regions which will become a plurality of transistors. Silicon oxide fills these slots and separates the transistor regions from the substrate. Orthogonal slots divide the semi-arrays into individual transistor active regions which are doped by one of N or P doping introduced into each active regions via the orthogonal slots and driven in to comprise the emitter and collector regions on respective sides of original substrate comprising the base regions. Metallization patterns complete electrical connections to the emitter base and collector regions and silicon oxide substantially covers the periphery of each active region for total isolation.

Abstract: Disclosed is an eight-mask twin-tub CMOS process which forms contiguous p- and n-tubs in a relatively lightly doped bulk region in a self-aligned manner using a single masking step. The process also forms the sources and drains of the p- and n-channel transistors with a single masking step by first nonselectively implanting p-type impurities into all source and drain regions and then selectively implanting n-type impurities into only the source and drain regions of the n-channel transistors in amounts sufficient to overcompensate the p-type impurities therein.

Abstract: A semiconductor device has a first semiconductor layer with a main surface and a second semiconductor layer forming a PN junction with the first semiconductor layer, the PN junction reaching the main surface. An insulating layer is formed on the main surface and has at least one window which at least exposes a part of the second semiconductor layer. A third semiconductor layer, which is the same conductivity type as the second semiconductor layer, is formed on a portion exposed in the window. A metal-semiconductor alloy layer is electrically connected to the third semiconductor layer. According to another aspect of the invention, a method of manufacturing the smiconductor device uses the steps of providing a first semiconductor layer with a main surface, making a second semiconductor layer to form a PN junction reaching the main surface of the first semiconductor layer, and forming an insulating layer with at least one window exposing at least a part of the second semiconductor layer on the main surface.

Abstract: A molten iron containing vessel includes a refractory fireproof inner lining of dolomite bricks and bauxite bricks. The lining includes magnesia bricks positioned between the dolomite and bauxite bricks, thereby avoiding contact reactions between the dolomite and bauxite. A gas permeable brick member extends through an end portion of the vessel for injecting a gas into the molten iron contained therein.

Abstract: A method for producing a MOSFET which includes the steps of forming a thick insulating layer having an inclined surface and surrounding the active region of a semiconductor substrate, forming a thin insulating layer on the active region, forming a gate electrode crossing the thin insulating layer and extending on the thick insulating layer, and forming a source region and a drain region in the active region in which method the step of forming the gate electrode includes the steps of forming a conductive layer on the thin insulating layer and thick insulating layer, forming a resist layer on the conductive layer selectively exposing the resist layer to an energy ray to define a gate electrode pattern area of which a portion above the inclined surface and above the end portions of the active region is wider than another portion above the middle portion of the active region developing the resist layer and selectively etching the conductive layer by using the developed resist layer as a mask.

Abstract: Processes for manufacturing insulated-gate semiconductor devices such as MOSFETs wherein the source and base regions and the source-to-base ohmic short are formed employing self-aligned masking techniques are disclosed. In the exemplary case of a MOSFET, the processes begin with a semiconductor wafer (such as silicon) including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. Through subsequent masking and etching steps, channels are etched through the polysilicon gate layer at least to the drain region. The un-etched portions define polysilicon gate electrodes spaced along the drain region. A two-stage polysilicon etch procedure is disclosed. An initial etch step produces relatively narrow channels. Unetched portions of the polysilicon layer are then used as masks to form a shorting extension of the device base region, preferably by ion implantation.

Abstract: A method for fabricating a semiconductor integrated circuit structure having a sub-micrometer length device element is described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. These semiconductor regions are designated to contain devices. At least one layer is formed over the device designated regions and etched to result in a patterned layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A controlled sub-micrometer thickness sidewall layer is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness sidewall layer portions of which extend across certain of the device regions. The desired pattern of PN junctions are now formed in the substrate using for example diffusion or ion implantation techniques with the controlled thickness sub-micrometer layer used as a mask.

Abstract: The invention makes it possible to manufacture silicon wafers having vertical p-n junctions as the basic material for solar cells. As a result of simultaneously adding certain dopants that act in the silicon crystal as donors and certain dopants that develop acceptor properties and also as a result of measures that result in a periodic change in the crystal growth from a low rate v.sub.n to a high rate v.sub.n, p- and n-conductive zones are produced in the silicon, each having a total length of from 5 to 2000 .mu.m.

Abstract: A method of liquid phase epitaxy is disclosed for growing a plurality of different layers on each of a plurality of semiconductor wafers during a single heating cycle. Each of a series of melts, each corresponding to a layer to be grown, is divided, in succession, into aliquant portions and a remainder portion. Each aliquant portion is contacted by one or more wafers, and epitaxial growth occurs as the temperature is lowered. Provision of a remainder portion enables a two-phase melt, and a wafer contacts only one distinct melt at a time.After a growth step, the next successive melt likewise is separated into aliquant portions and a remainder portion, the wafers are removed from the preceding melt chambers and placed in contact with the newly formed aliquant portions, and growth of another layer ensues from another drop in temperature. The process is repeated for each melt provided.Apparatus for carrying out the method also is described.

Abstract: A semiconductor memory device and a method of manufacturing the device wherein a field insulation is formed in a surface of a semiconductor body except for the source, drain and channel regions, a first floating gate is self-aligned to the channel region, a second gate insulated from the first floating gate covers the first floating gate and the first insulator having a width substantially same as the length of the channel region between the source and the drain regions.

Abstract: A process of fabricating high density CMOS integrated circuits having conductively interconnected wells. The conductive interconnection is provided by a buried conductor formed in combination with channel stops encircling each of the wells and prior to the fabrication of FET active devices at the surface of the wells. The channel stops, as provided by the process, are automatically aligned with and spaced apart from the source and drain regions of their respective FETs.

Abstract: A process and related product in which ohmic contacts are formed in semiconductor devices employing compound substrates such as gallium arsenide. In the disclosed embodiment, a germanium layer (18) is deposited in those areas (14) in which ohmic contact is required and is subsequently diffused into a layer 20 of the substrate during a conventional annealing step required to relieve damage caused to the substrate during a prior conventional ion implantation step. As a result of the diffusion of the germanium, good ohmic contact can be made by deposition of a conductive metal 26, such as gold. Thus, a common metalization step can be employed to form both the ohmic contact regions and rectifying contact regions used as gates in field effect transistors.

Abstract: A consumable heat retention shield for retaining the heat of the interior lining of a hot metal car includes a combustible framework having a bottom wall, upstanding walls and a flange, with the surface thereof that is to be directly exposed to the hot metal car covered with a layer of refractory material, with the shield being manually positioned on the hot metal car by workmen, and the shield consumable upon pouring of molten metal upon the shield and through the mouth of the hot metal car. Preferably, the shield has a metallic filler material in a cavity thereof to provide additional weight to the shield, which metallic filler material is compatable with the molten metal charged to the hot metal car.

Abstract: A drapable, consumable, heat retention shield for hot metal cars has a fibrous refractory sheet disposed between two metallic lattices, the lattices connected by fastening means to retain the sheet to form a panel having a bottom wall, upstanding side walls and a flange extending outwardly from the side walls. In one embodiment the metallic lattices substantially cover the fibrous refractory sheet, while in another embodiment cross strips of metallic lattices are used with a combustible supporting frame provided about the periphery of the fibrous refractory sheet to support the same.

Abstract: A steel ladle is provided with a burn resistant liner generally conforming to the inner contour of the ladel but spaced therefrom. A layer of sand is placed within the space between the ladle and liner to support the liner when loaded with a non-ferrous melt. The sand and the liner are retained within the ladle by a refractory cap extending between the upper edges of the liner and the ladle on top of the sand layer. A method of preparing a ladle to receive a non-ferrous melt involves lining the ladle interior with a burn resistant lining, supporting the lining on a sand layer disposed between the ladle interior and the lining, and retaining the sand and the liner within the ladle so they will not separate therefrom during pouring.

Abstract: Improved lead attachment method accommodates a situation wherein electrical signal leads must be connected to portions of a circuit operating at high temperatures such as 900.degree. F. or more and terminate in equipment operating at or near ambient temperatures. For example, in solid electrolyte oxygen sensors incorporating a tubular ceramic member, a connection wire which is sufficiently thick to resist wire breakage during normal handling has been found to be too thick to bond to a connection pad on the ceramic without having the bond crack during thermal cycling. With improved method, a thin wire is attached to a thicker one in a region where flexing cannot occur. At least the larger wire is shrunk-fit into a hole formed in the ceramic before firing, and then the thinner wire is bonded to the pad with a conductive paste which must also be fired.

Abstract: This invention relates to a process for conditioning the surfaces of natural and synthetic plastic materials for electroless plating of a metal coating thereon by exposing such materials to an atmosphere comprising an effective amount of ozone and thereafter contacting said exposed materials with an effective amount of a conditioning solvent, such as an aqueous solution of sodium, potassium or lithium hydroxide.

Abstract: A method for forming an isolation region on a semiconductor substrate which comprises steps of forming first a groove in said substrate, filling the groove with a first insulating film in a manner which may inevitably leave a gap between the wall of the groove and the each side of the first insulating film, forming a second insulating film on the surface of said substrate including said groove, and removing a surface layer of said second insulating film thereby forming an isolation region in the groove filled completely with the first and second insulating films.

Abstract: Disclosed is a process which is fully compatible with normal two layer polysilicon SNOS process and provides polysilicon parallel plate capacitors and silicon gate non-memory MOS transistors (diodes) for constructing therefrom an on-chip, dual polarity high voltage multiplier. From the polysilicon I layer deposited over a gate oxide, the polysilicon I resistor, the non-memory device gate and the capacitor lower plate are formed. Then, the resistor, non-memory device gate and active region and the periphery of the capacitor lower plate are covered with an isolation oxide. Next, a dielectric, e.g., oxide-nitride, and polysilicon II layers are formed over the structure. Polysilicon II is patterned into interconnect, gate for SNOS memory device and capacitor upper plate, the latter having a plurality of holes therein. The dielectric is formed into SNOS device gate insulator and the capacitor insulator, the latter having holes in registration with the holes in the capacitor upper plate.