Patents Examined by Gardner W. S. Swan
  • Patent number: 11011515
    Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: May 18, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qhalid Fareed, Naveen Tipirneni
  • Patent number: 11011621
    Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Ming Zhu
  • Patent number: 11004825
    Abstract: Provided is a semiconductor package of a package on package (PoP) type having an improved electromagnetic wave shielding property. The semiconductor package includes: a first sub-package including a first package base substrate on which a first semiconductor chip is mounted, and an electromagnetic wave shielding member having a top portion and side portions respectively at a top surface and side surfaces of the first sub-package, wherein a groove space extends inward from a bottom surface of the first sub-package; and a second sub-package including a second package base substrate in the groove space and on which a second semiconductor chip is mounted, wherein the second sub-package is connected to the first sub-package through an inter-package connection terminal attached to a first package connection pad at a bottom surface of the groove space of the first sub-package.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dong-ha Lee
  • Patent number: 10981779
    Abstract: A MEMS device and methods of forming are provided. A dielectric layer of a first substrate is patterned to expose conductive features and a bottom layer through the dielectric layer. A first surface of a second substrate is bonded to the dielectric layer and the second substrate is patterned to form a membrane and a movable element. A cap wafer is bonded to the second substrate, where bonding the cap wafer to the second substrate forms a first sealed cavity comprising the movable element and a second sealed cavity that is partially bounded by the membrane. Portions of the cap wafer are removed to expose the second sealed cavity to ambient pressure.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung Chang, Len-Yi Leu, Lien-Yao Tsai
  • Patent number: 10950510
    Abstract: A semiconductor device includes a base substrate, a protruding structure on the base substrate, a porous film on a side surface and an upper surface of the protruding structure, and an air gap between at least a part of the side surface of the protruding structure and the porous film.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok Han Park
  • Patent number: 10937849
    Abstract: An array substrate has a display area and a non-display area disposed at a periphery of the display area. The array substrate includes: a base substrate; at least one gate driver on array (GOA) circuit disposed on the base substrate and disposed in the non-display area; a planarization layer disposed on a side of the at least one GOA circuit facing away from the base substrate; and at least one electrostatic protection portion disposed on a surface of the planarization layer facing away from the base substrate and disposed in the non-display area. An orthographic projection of each GOA circuit on the base substrate is located within an outer boundary of an orthographic projection of a corresponding electrostatic protection portion on the base substrate.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 2, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Hongfei Cheng
  • Patent number: 10930618
    Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Won-young Kim
  • Patent number: 10910590
    Abstract: A novel thin film encapsulated OLED panel architecture and a method for making the panels with improved shelf life is disclosed. The OLED panel consists of a plurality of OLED pixels; each OLED pixel is individually hermetically sealed and isolated from its neighboring pixels. The organic stack of the OLED pixel is contained within its own hermetically sealed structure, achieved by making the structure on a barrier coated substrate and using a first barrier material as the grid and a second barrier for encapsulating the entire OLED pixel. The first barrier material provides the edge seal while the second barrier disposed over the pixel provides protection from top down moisture diffusion. By isolating and hermetically sealing individual pixels; any damage such as moisture and oxygen ingress due to defects or particles, delamination, cracking etc. can be effectively contained within the pixel thereby protecting other pixels in the panel.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: February 2, 2021
    Assignee: Universal Display Corporation
    Inventors: Siddharth Harikrishna Mohan, William E. Quinn, Ruiqing Ma, Emory Krall, Luke Walski
  • Patent number: 10910355
    Abstract: A bezel-free display comprises a display substrate and an array of pixels. Pixel rows and pixel columns are separated by row and column distances and connected by row and column lines, respectively. A column driver is electrically connected to each of the column lines and a row driver is electrically connected to each of the row lines. Row-connection lines are electrically connected to each of the row lines or row drivers. In certain embodiments, each pixel in the column of pixels closest to a display substrate edge is spatially separated from the edge by a distance less than or equal to the column distance. At least one row driver is spatially separated from the corresponding row by a distance less than the column or row distance, at least one column driver is spatially separated from the corresponding column by a distance less than the column or row distance, or both.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 2, 2021
    Assignee: X Display Company Technology Limited
    Inventors: Ronald S. Cok, Brook Raymond
  • Patent number: 10847515
    Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 24, 2020
    Inventors: Jae Jung Kim, Young Suk Chai, Sang Yong Kim, Hoon Joo Na, Sang Jin Hyun
  • Patent number: 10804320
    Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoonsung Han, Seung Pil Ko
  • Patent number: 10801710
    Abstract: An LED lighting device capable of discharging heat generated from a light emitting element to the outside the LED lighting device. An LED lighting device includes: a plurality of light emitting elements; a mounted substrate on which the light emitting elements are mounted; and an electrode portion configured to supply a current to the light emitting elements from outside the LED lighting device. On the mounted substrate, a wiring substrate is located. On the upper surface of the mounted substrate, the mounted substrate includes: a light emitting region in which the plurality of light emitting elements are mounted; an exposed region which is located on the outer side of the light emitting region and through which the upper surface of the mounted substrate is exposed; and a wiring region which is located on the outer side of the light emitting region and in which the wiring substrate is located.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: October 13, 2020
    Assignees: CITIZEN ELECTRONICS CO., LTD., CITIZEN WATCH CO., LTD.
    Inventors: Takashi Iino, Sadato Imai
  • Patent number: 10790351
    Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes: a voltage conducting layer, at least part of which is in a display area; a voltage connecting terminal in a peripheral circuit area, and a conductive lead in the peripheral circuit area. The conductive lead includes: a first annular portion, a second annular portion, and a plurality of bridging portions. The first annular portion is connected to the voltage conducting layer, the second annular portion surrounds the first annular portion and connected to the voltage connecting terminal, and a first end and a second end of each bridging portion are connected to the first annular portion and the second annular portion respectively.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 29, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Xiaowei Wang, Guoqing Zhang
  • Patent number: 10784339
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: transistor cells formed along a first surface at a front side of a semiconductor portion; a drain structure between the transistor cells and a second surface of the semiconductor portion opposite to the first surface, the drain structure forming first pn junctions with body regions of the transistor cells and including an emitter layer directly adjoining the second surface; and a metal drain electrode directly adjoining the emitter layer. An integrated concentration of activated dopants along a shortest line between the metal drain electrode and a closest doped region of a charge type of the body regions is at most 1.5E13 cm?2. Further semiconductor device embodiments are described.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: September 22, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Enrique Vecino Vazquez, Daniel Pobig, Franz Hirler, Manfred Pippan, Patrick Schindler
  • Patent number: 10749123
    Abstract: A system and method for the fabrication of high efficiency OLED devices and more specifically, the fabrication of OLED panels optically coupled with impact resistant, transparent structures which permit operation of the OLED panel while providing impact resistance. The OLED device can be built directly on an impact resistant transparent structure, or attached to an impact resistant transparent structure after it is built on other types of substrate. The impact resistant transparent structure can be a toughened layer, such as a glass layer, an energy absorption layer, such as Polycarbonate (PC), or a combination of both. The OLED device is configured to transmit light through the impact resistant transparent structure to the viewer, and the impact resistant transparent structure provides impact resistance for the OLED from the force of any impacting object.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: August 18, 2020
    Assignee: Universal Display Corporation
    Inventors: Mauro Premutico, Ruiqing Ma
  • Patent number: 10741636
    Abstract: A semiconductor structure and a method of fabricating thereof are provided. The semiconductor structure includes a substrate and a capacitor structure. The substrate has a first blind hole and a trench. The first blind hole communicates with the trench. The first blind hole has a first depth, and the trench has a second depth smaller than the first depth. The capacitor structure includes a first inner conductor, a first inner insulator, and an outer conductor. The first inner conductor is in the first blind hole. The first inner insulator surrounds the first inner conductor. The outer conductor has a first portion surrounding the first inner insulator and an extending portion extending from the first portion. The first portion is in the first blind hole, and the extending portion is in the trench. The first inner conductor is separated from the outer conductor by the first inner insulator.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tieh-Chiang Wu
  • Patent number: 10727450
    Abstract: A display apparatus includes a flexible substrate, a thin-film transistor unit, and a light-emitting unit. The flexible substrate includes a display area has a first area, a peripheral area which is adjacent to the display area, and a first penetrating portion corresponding to the first area. The thin-film transistor unit is in the display area and at least a portion of the peripheral area. The thin-film transistor unit includes a thin-film transistor and an insulation layer and has a second penetrating portion at a location corresponding to the first penetrating portion. The light-emitting unit is on the thin-film transistor unit and includes a pixel electrode, an intermediate layer including an emission layer, and a counter electrode.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jonghyun Yun, Junyoung Kim, Seunggyu Tae, Jongmoo Huh, Kwangsoo Lee, Sangcheon Han
  • Patent number: 10720596
    Abstract: The organic light emitting display panel includes a first electrode formed on a substrate, an organic light emitting layer formed on the first electrode, a second electrode formed on the organic light emitting layer, a front sealing layer formed on the second electrode, wherein the front sealing layer is formed by alternately laminating an inorganic barrier layer and an organic barrier layer at least once, and at least one capping layer formed between the lowest layer closest to the second electrode among a plurality of thin films of the front sealing layer and the second electrode and having a higher index of refraction than an index of refraction of the lowest layer.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: July 21, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Young-Dock Cho, Kwang-Yeon Lee, Heui-Dong Lee, Eun-Jung Park, Hong-Je Yun, Sang-Kyoung Moon
  • Patent number: 10714477
    Abstract: A p-channel tri-gate transistor has a silicon fin that protrudes from a bulk silicon substrate, a thin silicon-germanium active layer is formed on three sidewalls of the silicon fin, and a hole well is formed between the gate insulating film and the silicon fin in the active layer surrounded by the tri-gate by a valence band offset electric potential against the silicon fin for moving holes collected in the hole well along the active layer with a high hole-mobility. Thus, it is possible to have the effects of not only an ultra-high speed, low power operation, but also a body biasing through an integral structure of the silicon fin-body. The p-channel tri-gate transistor can be fabricated together with an n-channel FinFET transistor in one substrate by the same CMOS process.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: July 14, 2020
    Assignee: Gachon University of Industry-Academic Cooperation Foundation
    Inventors: Seongjae Cho, Eunseon Yu
  • Patent number: 10678098
    Abstract: A display apparatus comprises a first substrate comprising a first external surface and a first internal surface; a second substrate having a second external surface and a second internal surface facing the first internal surface of the first substrate; and a display unit disposed between the first and second substrates and comprising an array of pixels. The first substrate comprises a first side connecting the first external surface and the first internal surface. In a cross section perpendicular to the first external surface, the first side comprises a first straight region and a first curved region located between the first straight region and the first internal surface. The second substrate comprises a second side connecting the second external surface and the second internal surface. The second side comprises a second straight region and a second curved region located between the second straight region and the second internal surface.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: June 9, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyoengki Kim, Sangwook Sin, Jaeyoung Shin, Seungjoon Yoo, Jaeman Lee, Hyunsoo Lee, Beomjun Cheon, Gwangjoon Hong