Patents Examined by Gardner W. S. Swan
  • Patent number: 11360044
    Abstract: The present invention concerns a sensitive field effect device (100) comprising a semiconductor channel (110), a source electrode (120) connected to said semiconductor channel (110), a drain electrode (130) connected to said semiconductor channel (110), such that said semiconductor channel (110) is interposed between said source electrode (120) and said drain electrode (130), a gate electrode (140) and a dielectric layer (150) interposed between said gate electrode (140) and said semiconductor channel (110), characterized in that said semiconductor channel (110) is a layer and is made of an amorphous oxide and in that said sensor means (170, 171, 172, 173, 174, 175, 175) are configured to change the voltage between said gate electrode (140) and said source electrode (120) upon a sensing event capable of changing their electrical state. The present invention also concerns a sensor and a method for manufacturing said field effect device (100).
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: June 14, 2022
    Assignees: Universidade Nova de Lisboa, Alma Mater Studiorum—Universita di' Bologna
    Inventors: Rodrigo Ferräo De Paiva Martins, Pedro Miguel Cândido Barquinha, Elvira Maria Correia Fortunato, Tobias Cramer, Beatrice Fraboni
  • Patent number: 11342439
    Abstract: A semiconductor device and a semiconductor structure are disclosed. The semiconductor device includes a substrate, a first III-V compound layer, a second III-V compound layer, a source, a drain and a gate stack structure. The first III-V compound layer is disposed on the substrate. The second III-V compound layer is disposed on the first III-V compound layer. The source and the drain are disposed on opposite sidewall boundaries of the second III-V compound layer. The gate stack structure is disposed on the second III-V compound layer. The gate stack structure includes a first gate and a second gate. The first gate is disposed on the second III-V compound layer. The second gate is disposed on and electrically isolated from the first gate. The second gate is electrically coupled to the source.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 24, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Vivek Ningaraju, Po-An Chen
  • Patent number: 11335720
    Abstract: To suppress variation in transistor characteristics due to charging damage to relieve restrictions on design necessary for avoiding the charging damage and improve the degree of freedom in design for increasing semiconductor integration. A semiconductor device includes a vertical electrode formed in a vertical hole extending from an opening portion toward a portion to be connected in a thickness direction of a base, and having a structure in which a barrier metal film and a conductive material are stacked sequentially from a side close to an insulating film exposed to the vertical hole, and a low-resistance film provided to lie between the barrier metal film and the insulating film except a vicinity of the portion to be connected, and having a lower resistance value than a resistance value of the insulating film.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 17, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Takushi Shigetoshi
  • Patent number: 11309224
    Abstract: A semiconductor device includes a flexible wiring substrate. The wiring substrate includes at least two mounting portions and at least one connecting portion. The mounting portions are stacked spaced apart from each other. Each connecting portion is bent to connect two mounting portions that are adjacent in a stacking direction. The semiconductor device further includes at least one semiconductor chip mounted on at least one of the at least two mounting portions and a plurality of conductive connecting members connecting the mounting portions to each other in the stacking direction.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: April 19, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yasuyoshi Horikawa, Yoshihiro Ihara, Yoshihiro Kita, Hikaru Tanaka
  • Patent number: 11309329
    Abstract: A NOR-type three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a substrate, and laterally alternating sequences of respective active region pillars and respective memory stack structures. Each laterally alternating sequence is electrically isolated from the electrically conductive layers by a respective blocking dielectric layer at each level of the electrically conductive layers. Each memory stack structures include a memory film and a semiconductor channel material portion that vertically extend through the vertically alternating stack. The active region pillars include an alternating sequence of source pillar and drain pillars.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: April 19, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Hanan Borukhov
  • Patent number: 11295990
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 11289569
    Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Chieh Chan, Chung-Hui Chen
  • Patent number: 11289414
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim
  • Patent number: 11282840
    Abstract: Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 22, 2022
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Valery Axelrad
  • Patent number: 11282896
    Abstract: An electroluminescent display apparatus includes: a substrate including: first to third subpixels, a circuit device layer including a driving thin-film transistor respectively in each of the first to third subpixels on the substrate, a first electrode respectively in each of the first to third subpixels, a light-emitting layer on the first electrodes, and a second electrode on the light-emitting layer, wherein the first electrode of the first subpixel includes: a first lower electrode, and a first upper electrode, wherein the first electrode of the second subpixel includes: a second lower electrode, and a second upper electrode, wherein a distance between the first lower electrode and the first upper electrode differs from a distance between the second lower electrode and the second upper electrode, and wherein the first lower electrode and the first upper electrode are electrically connected to each other through a first contact electrode therebetween.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: March 22, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Ho-Jin Kim, Gyungmin Kim, Sul Lee
  • Patent number: 11270952
    Abstract: A semiconductor structure includes a semiconductor strip in a seal ring area. The semiconductor structure further includes a dielectric structure extending into the semiconductor strip, wherein a plurality of metal structures and a plurality of via structures stack over the dielectric structure to form a seal ring structure.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shan Wang, Shun-Yi Lee
  • Patent number: 11271061
    Abstract: An organic light-emitting display apparatus includes: a display unit including an organic light-emitting element, a driving transistor electrically connected to the organic light-emitting element, and a capacitor; and a pad unit connected to the display unit, the capacitor including: a first conductive layer disposed on a substrate; a second conductive layer interposed between the substrate facing a first surface of the first conductive layer; and a third conductive layer disposed facing a second surface of the first conductive layer opposing the first surface of the first conductive layer, the third conductive layer being electrically connected to the second conductive layer.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: March 8, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seulki Kim, Seungsok Son, Jungkyoung Cho
  • Patent number: 11264460
    Abstract: The present disclosure provides methods for forming a channel structure in a film stack for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and a channel structure formed in the film stack, wherein the channel structure is filled with a channel layer and a protective blocking layer, wherein the channel layer has a gradient dopant concentration along a vertical stacking of the film stack.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 1, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Arvind Kumar, Sanjeev Manhas, Mahendra Pakala, Ellie Y. Yieh
  • Patent number: 11251127
    Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Te Ho, Ming-Chung Liang, Chien-Chih Chiu, Chien-Han Chen
  • Patent number: 11217772
    Abstract: A display apparatus including a base layer including a display region and a non-display region; display elements on the display region and including a first electrode, a light emitting layer, and a second electrode on the light emitting layer; and an upper layer on the display elements, wherein the upper layer includes a first organic layer contacting the second electrode; a first inorganic layer contacting the first organic layer; a second organic layer contacting the first inorganic layer; and a second inorganic layer contacting the second organic layer, wherein the first inorganic layer includes a first and second area, the first area having a refractive index of about 1.60 to about 1.65 with respect to a wavelength of about 633 nm, wherein the first area has a uniform thickness, and wherein a thickness of the second area decreases as a distance from the display region increases.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: January 4, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Soyeon Jeong, Jaehyun Kim, Daesang Yun, Cheho Lee
  • Patent number: 11217555
    Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Jui Huang, Chien Ling Hwang, Chih-Wei Lin, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11211323
    Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Shiao-Chian Yeh, Hong-Jang Wu, Kuei-Shun Chen
  • Patent number: 11205741
    Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: December 21, 2021
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Juanita Kurtin, Brian Theobald, Matthew J. Carillo, Oun-Ho Park, Georgeta Masson, Steven M. Hughes
  • Patent number: 11205770
    Abstract: According to a flexible light-emitting device production method of the present disclosure, after an intermediate region (30i) and a flexible substrate region (30d) of a plastic film (30) of a multilayer stack (100) are divided, the interface between the flexible substrate region (30d) and a glass base (10) is irradiated with lift-off light. The multilayer stack (100) is separated into the first portion (110) and the second portion (120) while the multilayer stack (100) is kept in contact with the stage (210). The first portion (110) includes a plurality of light-emitting devices (1000) which are in contact with the stage (210). The light-emitting devices (1000) include a plurality of functional layer regions (20) and the flexible substrate region (30d). The second portion (120) includes the glass base (10) and the intermediate region (30i).
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: December 21, 2021
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Katsuhiko Kishimoto, Kohichi Tanaka
  • Patent number: 11195816
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes a plurality of integrated circuits, a first encapsulant, a first redistribution structure, a plurality of conductive pillars, a second redistribution structure, a second encapsulant and a third redistribution structure. The first encapsulant encapsulates the integrated circuits. The first redistribution structure is disposed over the first encapsulant and electrically connected to the integrated circuits. The conductive pillars are disposed over the first redistribution structure. The conductive pillars are disposed between and electrically connected to the first and second redistribution structures. The second encapsulant encapsulates the conductive pillars and is disposed between the first redistribution structure and second redistribution structure.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee