Abstract: A NOR-type three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a substrate, and laterally alternating sequences of respective active region pillars and respective memory stack structures. Each laterally alternating sequence is electrically isolated from the electrically conductive layers by a respective blocking dielectric layer at each level of the electrically conductive layers. Each memory stack structures include a memory film and a semiconductor channel material portion that vertically extend through the vertically alternating stack. The active region pillars include an alternating sequence of source pillar and drain pillars.

Abstract: A semiconductor device includes a flexible wiring substrate. The wiring substrate includes at least two mounting portions and at least one connecting portion. The mounting portions are stacked spaced apart from each other. Each connecting portion is bent to connect two mounting portions that are adjacent in a stacking direction. The semiconductor device further includes at least one semiconductor chip mounted on at least one of the at least two mounting portions and a plurality of conductive connecting members connecting the mounting portions to each other in the stacking direction.

Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package.

Abstract: An electroluminescent display apparatus includes: a substrate including: first to third subpixels, a circuit device layer including a driving thin-film transistor respectively in each of the first to third subpixels on the substrate, a first electrode respectively in each of the first to third subpixels, a light-emitting layer on the first electrodes, and a second electrode on the light-emitting layer, wherein the first electrode of the first subpixel includes: a first lower electrode, and a first upper electrode, wherein the first electrode of the second subpixel includes: a second lower electrode, and a second upper electrode, wherein a distance between the first lower electrode and the first upper electrode differs from a distance between the second lower electrode and the second upper electrode, and wherein the first lower electrode and the first upper electrode are electrically connected to each other through a first contact electrode therebetween.

Abstract: Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

Abstract: A semiconductor structure includes a semiconductor strip in a seal ring area. The semiconductor structure further includes a dielectric structure extending into the semiconductor strip, wherein a plurality of metal structures and a plurality of via structures stack over the dielectric structure to form a seal ring structure.

Abstract: An organic light-emitting display apparatus includes: a display unit including an organic light-emitting element, a driving transistor electrically connected to the organic light-emitting element, and a capacitor; and a pad unit connected to the display unit, the capacitor including: a first conductive layer disposed on a substrate; a second conductive layer interposed between the substrate facing a first surface of the first conductive layer; and a third conductive layer disposed facing a second surface of the first conductive layer opposing the first surface of the first conductive layer, the third conductive layer being electrically connected to the second conductive layer.

Abstract: The present disclosure provides methods for forming a channel structure in a film stack for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and a channel structure formed in the film stack, wherein the channel structure is filled with a channel layer and a protective blocking layer, wherein the channel layer has a gradient dopant concentration along a vertical stacking of the film stack.

Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

Abstract: A display apparatus including a base layer including a display region and a non-display region; display elements on the display region and including a first electrode, a light emitting layer, and a second electrode on the light emitting layer; and an upper layer on the display elements, wherein the upper layer includes a first organic layer contacting the second electrode; a first inorganic layer contacting the first organic layer; a second organic layer contacting the first inorganic layer; and a second inorganic layer contacting the second organic layer, wherein the first inorganic layer includes a first and second area, the first area having a refractive index of about 1.60 to about 1.65 with respect to a wavelength of about 633 nm, wherein the first area has a uniform thickness, and wherein a thickness of the second area decreases as a distance from the display region increases.

Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.

Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.

Abstract: According to a flexible light-emitting device production method of the present disclosure, after an intermediate region (30i) and a flexible substrate region (30d) of a plastic film (30) of a multilayer stack (100) are divided, the interface between the flexible substrate region (30d) and a glass base (10) is irradiated with lift-off light. The multilayer stack (100) is separated into the first portion (110) and the second portion (120) while the multilayer stack (100) is kept in contact with the stage (210). The first portion (110) includes a plurality of light-emitting devices (1000) which are in contact with the stage (210). The light-emitting devices (1000) include a plurality of functional layer regions (20) and the flexible substrate region (30d). The second portion (120) includes the glass base (10) and the intermediate region (30i).

Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes a plurality of integrated circuits, a first encapsulant, a first redistribution structure, a plurality of conductive pillars, a second redistribution structure, a second encapsulant and a third redistribution structure. The first encapsulant encapsulates the integrated circuits. The first redistribution structure is disposed over the first encapsulant and electrically connected to the integrated circuits. The conductive pillars are disposed over the first redistribution structure. The conductive pillars are disposed between and electrically connected to the first and second redistribution structures. The second encapsulant encapsulates the conductive pillars and is disposed between the first redistribution structure and second redistribution structure.

Abstract: Provided is a resistance element, including: a semiconductor substrate; a first insulating film stacked on the semiconductor substrate; a resistance layer selectively stacked on the first insulating film; a first auxiliary film separated from the resistance layer; a second auxiliary film separated from the resistance layer in a direction different from that of the first auxiliary film; a second insulating film stacked on the first insulating film to cover the resistance layer, and the first auxiliary film and the second auxiliary film; a first electrode connected to the resistance layer and stacked on the second insulating film disposed on an upper side of the first auxiliary film; and a second electrode connected to the resistance layer by being separated from the first electrode and stacked on the second insulating film on the upper side of the second auxiliary film.

Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.

Abstract: According to a method for producing a flexible OLED device of the present disclosure, a multilayer stack (100) is provided, the multilayer stack including a base (10), a functional layer region (20) which includes a TFT layer and an OLED layer, a flexible film (30) provided between the base and the functional layer region and supporting the functional layer region, and a release layer (12) provided between the flexible film and the base and bound to the base. The release layer is irradiated with lift-off light (216) transmitted through the base, whereby the flexible film is delaminated from the release layer. The release layer is made of an alloy of aluminum and silicon.