Abstract: An organic light emitting diode (OLED) display device and a method of manufacturing the same. The device includes a substrate, a thin film transistor (TFT) on the substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode, a first pixel electrode coupled to one of the source and drain electrodes, a rough portion on the first pixel electrode, a second pixel electrode on the rough portion and having a rough pattern, an intermediate layer on the second pixel electrode including an organic emission layer (EML), and an opposing electrode on the intermediate layer.

Abstract: An EL light-emitting element in which a lower electrode layer, an EL layer, and an upper electrode layer are stacked is formed on a substrate, and a wiring is formed on a counter substrate. Further, the substrate and the counter substrate are bonded so that the wiring is in physical contact with the upper electrode layer of the EL element. Accordingly, the wiring can serve as an auxiliary wiring for increasing conductivity of the upper electrode layer. With such an auxiliary wiring, a potential drop due to the resistance of the upper electrode layer can be suppressed even in the light-emitting device whose light-emitting portion is large.

Abstract: A method of fabricating a semiconductor structure. The method includes forming a dummy structure over a semiconductor body. The method further includes depositing an inter-layer dielectric (ILD) over the semiconductor body. The method further includes removing a dummy material of the dummy structure to form an opening in the ILD. The method further includes filling the opening with a dielectric material to form a dielectric structure. The method further includes stacking a plurality of interconnect elements over the dielectric structure.

Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element.

Abstract: The present disclosure relates to the technical field of semiconductor processes and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate containing a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer to cover the gate lines; planarizing the second dielectric layer; forming an insulating buffer material layer; patterning the insulating buffer material layer to form a patterned insulating buffer layer containing multiple separate portions, each separate portion extending to intersect one or more gate lines; selectively growing a graphene layer on the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the second dielectric layer; and forming an upper gate electrode layer on the third dielectric layer.

Abstract: An epitaxial layer is formed by epitaxy on a base substrate at a front side. From opposite to the front side, at least a portion of the base substrate is removed, wherein the base substrate is completely removed or a remnant base section has a thickness of at most 20 ?m. Dopants of a first charge type are implanted from opposite of the front side into an implant layer of the epitaxial layer. A metal drain electrode is formed opposite to the front side. At least the implant layer is heated to a temperature not higher than 500° C. The heating activates only a portion of the implanted dopants in the implant layer. After heating, an integrated concentration of activated dopants along a shortest line between the metal drain electrode and a closest doped region of a second, complementary charge type is at most 1.5E13 cm?2.

Abstract: A power semiconductor device has a metal molded body forming a first connecting conductor. From a first main surface of the metal molded body there is a first recess having a first base in which a first power semiconductor component is arranged which faces the first base and is connected in an electrically conductive manner. From a second main surface of the metal molded body, a second recess has a second base, and a second power semiconductor component is arranged with the first contact surface thereof associated with the second base connected in an electrically conductive manner to this base. An insulating material layer is on both main surfaces, filling and completely covering the recess, wherein the first insulating layer has an electrically conductive first via which connects a second contact surface of the first power semiconductor component in an electrically conductive manner to a first conducting surface arranged on the first insulating layer.

Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.

Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.

Abstract: A semiconductor device includes an interconnect layer on an inter-layer dielectric (ILD) structure. The ILD structure includes: first contacts, extending through the ILD structure, electrically connected to corresponding first components located in a floor structure underlying the ILD structure; at least one second component located within the ILD structure and spaced from a surface of the ILD structure (in a direction perpendicular to a plane of the ILD structure) a distance which is less than a thickness of the ILD structure; and second contacts directly contacting corresponding first regions of the at least one second component. The interconnect layer includes: first metallization segments which directly contact corresponding ones of the first contacts; and second metallization segments located over a second region of the at least one second component, a width of the second metallization segments being less than a width of the first metallization segments.

Abstract: A method for manufacturing an organic EL apparatus includes forming an organic EL element and a mounting terminal on a substrate of an element substrate as a first substrate, forming sealing films so as to cover at least the organic EL element and the mounting terminal, adhering a sealing substrate as a second substrate with respect to the element substrate using a filler, and etching the sealing films so as to expose at least a part of the mounting terminal, in which, in the etching of the sealing films, the second substrate, which is formed with a composition which reacts with an etching gas and vaporizes, or a protective member, which covers at least a part of the second substrate, is used as a mask.

Abstract: The amount of water and hydrogen contained in an oxide semiconductor film is reduced, and oxygen is supplied sufficiently from a base film to the oxide semiconductor film in order to reduce oxygen deficiencies. A stacked base film is formed, a first heat treatment is performed, an oxide semiconductor film is formed over and in contact with the stacked base film, and a second heat treatment is performed. In the stacked base film, a first base film and a second base film are stacked in this order. The first base film is an insulating oxide film from which oxygen is released by heating. The second base film is an insulating metal oxide film. An oxygen diffusion coefficient of the second base film is smaller than that of the first base film.

Abstract: An organic device, including semiconducting polymers processed from a solution cast on one or more dielectric layers on a substrate; and electrical contacts to the semiconducting polymers, wherein the substrate and the one or more dielectric layers are flexible and the semiconducting polymers are aligned. The one or more dielectric layers can increase mobility of the semiconducting polymers and/or alignment of the semiconducting polymers with one or more of the nanogrooves in the dielectric layers.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

Abstract: A display substrate having a black matrix with a curved surface, a method for manufacturing the same and a display device are provided. The display substrate includes a black matrix disposed between adjacent pixels, wherein a sidewall of the black matrix is a concave curved surface. During the formation of a color film, since the sidewall of the black matrix is formed as a concave curved surface, color film droplets in one sub-pixel may return into the sub-pixel along the curved surface while splashing to the sidewall of the black matrix, thereby the contamination to adjacent pixels caused by the droplets splashing may be avoided, and a yield of the substrate may be ensured.

Abstract: The present invention provides a substrate (1) with a bulk layer (3) and a buffer layer (4) having a thickness of less than 2 ?m arranged on the bulk layer (3) for growth of a multitude of nanowires (2) oriented in the same direction on a surface (5) of the buffer layer (4). A nanowire structure, a nanowire light emitting diode comprising the substrate (1) and a production method for fabricating the nanowire structure is also provided. The production method utilizes non-epitaxial methods for forming the buffer layer (4).

Abstract: A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit.

Abstract: Embodiments of a microelectronic packaged device and methods of making are provided, where the microelectronic packaged device includes a system package comprising a first die and a second die, wherein the first die and the second die are laterally positioned to one another, and the first die and the second die are laterally separated from one another by mold compound; and a conductive trace formed between a first conductive surface on an exposed surface of the first die and a second conductive surface on an exposed surface of the second die, wherein the conductive trace is laser sintered directly on the first conductive surface, on a portion of the exposed surface of the first die, on a portion of a top surface of the mold compound, on a portion of the exposed surface of the second die, and on the second conductive surface.

Abstract: A MEMS device and methods of forming are provided. A dielectric layer of a first substrate is patterned to expose conductive features and a bottom layer through the dielectric layer. A first surface of a second substrate is bonded to the dielectric layer and the second substrate is patterned to form a membrane and a movable element. A cap wafer is bonded to the second substrate, where bonding the cap wafer to the second substrate forms a first sealed cavity comprising the movable element and a second sealed cavity that is partially bounded by the membrane. Portions of the cap wafer are removed to expose the second sealed cavity to ambient pressure.

Abstract: A semiconductor structure includes a semiconductor substrate, a layer of electrically insulating material above the semiconductor substrate, and a layer of semiconductor material above the layer of electrically insulating material. A first transistor includes a first source region, a first drain region, and a first channel region formed in the semiconductor substrate, a first gate insulation layer positioned above the first channel region, and an electrically conductive first gate electrode, wherein the first gate insulation layer includes a first portion of the electrically insulating material. A second transistor includes a second source region, a second drain region, and a second channel region formed in the layer of semiconductor material, a second gate insulation layer positioned above the second channel region, and an electrically conductive second gate electrode, wherein a second portion of the layer of electrically insulating material is positioned below the second channel region.