Patents Examined by Gary Portka
  • Patent number: 9678666
    Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: June 13, 2017
    Assignee: INTEL CORPORATION
    Inventors: Blaise Fanning, Mark A. Schmisseur, Raymond S. Tetrick, Robert J. Royer, Jr., David B. Minturn, Shane Matthews
  • Patent number: 9678873
    Abstract: In one embodiment, a computer-implemented method includes detecting a cache miss for a cache line. A resource is reserved on each of one or more remote computing nodes, responsive to the cache miss. A request for a state of the cache line on the one or more remote computing nodes is broadcast to the one or more remote computing nodes, responsive to the cache miss. A resource credit is received from a first remote computing node of the one or more remote computing nodes, responsive to the request. The resource credit indicates that the first remote computing node will not participate in completing the request. The resource on the first remote computing node is released, responsive to receiving the resource credit from the first remote computing node.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: June 13, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Garrett M. Drapala, Vesselina K. Papazova, Robert J. Sonnelitter, III
  • Patent number: 9665284
    Abstract: In a distributed storage system, a method for extending a number N of data node devices comprises a server receives an instruction of adding X new data nodes into the distributed storage system. Then, the server obtains a number M of the all partitions included in a hash ring and determines that M/(N+X) is lower than a preset threshold. The hash ring is organized according to a distributed hash table (DHT), and includes a plurality of partitions. Each partition is mapping to a data node. Based upon the determination, the server generates new partitions by multiplying partitions mapping to each data node, based upon the determination. After storing mapping relationship between the new partitions and the X new data nodes, the server adds the X new data nodes into the distributed storage system.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: May 30, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Feng Zhang
  • Patent number: 9665311
    Abstract: Systems, methods and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of a storage device of the storage system, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including making specific logical addresses of a logical address space unavailable to a host. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the detecting, the performing, or both are performed by the storage device, or by one or more subsystems of the storage system distinct from the storage device, or by the host.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: May 30, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Allen Samuels, Warren Fritz Kruger, Linh Tien Truong
  • Patent number: 9658784
    Abstract: A computer-implemented method according to one embodiment includes collecting, by the computer, performance data corresponding to a tape drive and/or a magnetic tape head. The performance data is stored in memory, and used by the computer to perform problem analysis. A computer-implemented method according to another embodiment includes collecting, by the computer, performance data corresponding to a tape drive and/or a magnetic tape head. The collected performance data is condensed to reduce a size of the collected performance data. The condensed performance data is stored in memory, and used to perform problem analysis.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: May 23, 2017
    Assignee: International Business Machines Corporation
    Inventors: Said A. Ahmad, W. Stanley Czarnecki, Ernest S. Gale, Icko E. T. Iben, Josephine F. Kubista
  • Patent number: 9652153
    Abstract: Systems, methods and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of a storage device of the storage system, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including reducing a count of logical addresses of a logical address space available to a host. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the detecting, the performing, or both are performed by the storage device, or by one or more subsystems of the storage system distinct from the storage device, or by the host.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: May 16, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Allen Samuels, Warren Fritz Kruger, Linh Tien Truong
  • Patent number: 9645754
    Abstract: In a data protection field, a method for storing data in a data deduplication system, comprising: obtaining data chunks achieved from data deduplication; assigning the data chunks to at least one group; recording grouping information of the data chunks; with respect to each group, calculating parity data chunks based on data chunks in the group, where the parity data chunks are used for, in response to a data chunk in the group being damaged, causing the damaged data chunk to be recovered on the basis of other data chunks in the group and parity data chunks of the group; and storing the calculated parity data chunks. Also provided is an apparatus for storing data and a data deduplication system. The technical solution provided herein facilitates occupying as little physical storage space as possible while reducing the risk of the spread of data loss caused by the data deduplication technology.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Yan Xin Li, Yu Meng Li, Michael G. Sisco, Xin Xu
  • Patent number: 9645945
    Abstract: Fill partitioning of a shared cache is described. In an embodiment, all threads running in a processor are able to access any data stored in the shared cache; however, in the event of a cache miss, a thread may be restricted such that it can only store data in a portion of the shared cache. The restrictions to storing data may be implemented for all cache miss events or for only a subset of those events. For example, the restrictions may be implemented only when the shared cache is full and/or only for particular threads. The restrictions may also be applied dynamically, for example, based on conditions associated with the cache. Different portions may be defined for different threads (e.g. in a multi-threaded processor) and these different portions may, for example, be separate and non-overlapping. Fill partitioning may be applied to any on-chip cache, for example, a L1 cache.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: May 9, 2017
    Assignee: Imagination Technologies Limited
    Inventor: Jason Meredith
  • Patent number: 9627062
    Abstract: There is provided a memory unit that comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to a first local bit line and a second local bit line by respective first and second access transistors, and each memory cell being associated with a word line configured to control the first and second access transistors of the memory cell. The first and second local bit lines of each memory cell group being operatively connected to respective first and second column bit lines by respective first and second group access switches, the first group access switch being configured to be controlled by the second column bit line, and the second group access switch being configured to be controlled by the first column bit line.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: April 18, 2017
    Assignee: SURECORE LIMITED
    Inventor: Andrew Pickering
  • Patent number: 9619421
    Abstract: A flash memory drive comprising: a male USB connector; a female USB connector; a flash memory chip to store file data; a computing processor, operatively connected to the flash memory chip, to manage transfers of data to and from the flash memory chip; and a changeover switch, operatively connected to the computing processor, to connect the computing processor to one of the male USB connector and the female USB connector; wherein there is no data communication link between the male USB connector and the female USB connector when the changeover switch is connected to one of the male USB connector and the female USB connector.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: April 11, 2017
    Inventor: Israel Hershler
  • Patent number: 9612961
    Abstract: Techniques described herein generally include methods and systems related to cache partitioning in a chip multiprocessor. Cache-partitioning for a single thread or application between multiple data sources improves energy or latency efficiency of a chip multiprocessor by exploiting variations in energy cost and latency cost of the multiple data sources. Partition sizes for each data source may be selected using an optimization algorithm that minimizes or otherwise reduces latencies or energy consumption associated with cache misses.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 4, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9600206
    Abstract: Storage access requests, such as write requests, are received from a virtual machine. A storage request processing module updates one of multiple virtual disks as directed by each of the storage access requests, and a replication management module stores information associated with each storage access request in one of multiple logs. The logs can be transferred to a recovery device at various intervals and/or in response to various events, which results in switching logs so that the replication management module stores the information associated with each storage access request in a new log and the previous (old) log is transferred to the recovery device. During this switching, request ordering for write order dependent requests is maintained at least in part by blocking processing of the information associated with each storage access request.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: March 21, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sriravi Kotagiri, Rahul Shrikant Newaskar
  • Patent number: 9600200
    Abstract: Exemplary methods for caching data in a cache device include determining characteristics of a plurality of file extents associated with a plurality of files stored in a random access memory (RAM) device. In one embodiment, the methods include deferring caching of the stored plurality of file extents in a cache device until a predetermined condition has occurred. According to one embodiment, the methods include, in response to determining the predetermined condition has occurred, packing a first portion of the plurality of file extents into a first cache unit based on the characteristics of the file extents, wherein file extents of the first cache unit are likely to be accessed within a predetermined period of time and evicted together from the cache device. The methods further include caching the first cache unit in the cache device and removing the cached file extents from the RAM device.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: March 21, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Grant Wallace, Philip Shilane
  • Patent number: 9600410
    Abstract: Providing a RRAM based memory storage device that has a NAND memory type architecture with a configurable page size. In an embodiment, two memory registers can be used to access and transfer data stored in the storage device to a host. A memory controller on the storage device can determine a page size of the host, and alternately transfer data from the first register and then the second register until an amount of data transferred equals the page size of the host. The memory controller can send the data to the host as if the data belonged to one page transfer. In this way, the memory controller creates a virtualized page size based on the requirements of the host.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 21, 2017
    Assignee: CROSSBAR, INC.
    Inventors: Hagop Nazarian, Cliff Zitlaw
  • Patent number: 9601205
    Abstract: A write method of a storage device including at least one nonvolatile memory device and a memory controller controlling the nonvolatile memory device includes dividing write data into a plurality of page data groups, each page data group including multiple bits of data; encoding the divided page data groups using different binary codes, respectively; mapping the encoded page data groups; programming, in first memory cells connected to one word line, programming states to which binary values of each of the mapped encoded page data groups are mapped, such that, the plurality of page data groups correspond respectively to a plurality of read voltage levels, and for each of the plurality of page data groups, the page data group can be read by performing a single read operation on the first memory cells using the read voltage level corresponding to the page data group.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: March 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Younggeon Yoo, Junjin Kong, Hong Rak Son
  • Patent number: 9594684
    Abstract: A method for temporarily storing data and a storage device is provided. The method for temporarily storing data is applied to the storage device, and the storage device includes a source agent and a target agent. The method includes: sending, by the source agent, a data obtaining request to the target agent; receiving, by the source agent, target data that is corresponding to the data obtaining request and is returned by the target agent; determining, by the source agent, whether a snooping request that is for the target data and sent by the target agent is received after the data obtaining request is sent and before the target data is received, where the snooping request indicates that the target agent is simultaneously processing an obtaining request from another source agent for the target data; and if the snooping request is received, discarding, by the source agent, the target data.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: March 14, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Kejia Lan, Yongbo Cheng, Chenghong He
  • Patent number: 9563554
    Abstract: Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations. Persistent storage may be maintained by systems with or without memory management units.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 7, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jared E. Hulbert, John C. Rudelic, Hongyu Wang
  • Patent number: 9563382
    Abstract: Methods, systems, and computer readable media for providing a flexible host memory buffer are disclosed. One method includes allocating an amount of host memory as a host memory buffer accessible by a solid state drive (SSD) as a cache for SSD data. The method further includes caching data from the solid state drive in the host memory buffer. The method further includes monitoring utilization of the host memory buffer. The method further includes dynamically increasing or decreasing the amount of host memory allocated for the host memory buffer based on the utilization.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: February 7, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Judah Gamliel Hahn, Eran Erez, Sebastien Andre Jean
  • Patent number: 9563559
    Abstract: Some embodiments of the inventive subject matter are directed to operations that include determining that an access request to a computer memory results in a cache miss. In some examples, the operations further include determining an amount of cache resources used to service additional cache misses that occurred within a period prior to the cache miss. Furthermore, in some examples, the operations further include servicing the access request to the computer memory based, at least in part, on the amount of the cache resources used to service the additional cache misses within the period prior to the cache miss.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Hong L. Hua, William A. Maron, Mysore S. Srinivas
  • Patent number: 9557923
    Abstract: An apparatus for migrating data in a tiered storage architecture includes one or more processors and one or more memory devices coupled to the processors and storing instructions for execution by the processors. The instructions cause the one or more processors to: track temperature (i.e., frequency of access) of data blocks in a tiered storage architecture; generate heat maps indicating the temperature of the data blocks across different time intervals; process the heat maps using an image processing algorithm; compress the heat maps to reduce the size of the heat maps; compare the heat maps from the time intervals to identify temperature patterns occurring over time; predict, from the temperature patterns, when selected data blocks will change in temperature; and migrate the selected data blocks between tiers of the tiered storage architecture in anticipation of their changes in temperature.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Bish, Gregory E. McBride, David C. Reed, Richard A. Welp