Abstract: A self-tuning and efficient computer method is disclosed for the management of virtual storage applicable to dedicated real-time computer systems. This method interposes a layer between the application and the real-time computer system to form a two-layered structure to meet an application's request for virtual storage (i.e. buffer request). The method adds a real-time system's slower allocation (second layer) to guarantee the creation of all other buffers during one real-time period. The self-tuning first layer is checked first to satisfy a buffer request, while the untuned second layer is entered to create a buffer when the first layer fails; either the request size is not yet tuned, or the pre-allocated buffers have run out. These entrances to the second layer provide a monitoring mechanism from which a new pre-allocation definition, based on the system usage history, is derived to tune the first layer at the next initialization time.

Abstract: A centralized supervisory control system allowing a centralized supervisory control center exactly to grasp information about failures and other events occurring in a plurality of supervised apparatuses, the center being also notified of time-of-day indications corresponding to such occurrences. Each of the supervised apparatus turns its information into blocks for output to an intermediate control apparatus. The intermediate control apparatus continuously collects such status data from the supervised apparatuses and compares the data with the status data currently held in its memory. If the latest status data from a given supervised apparatus are found to contain a deviation from the old data, the latest data are stored in memory along with a time-of-day indication corresponding to the deviation. The latest status data and the time-of-day indication are sent to the centralized supervisory control center.

Abstract: This invention relates to a protocol implemented in a communication system for exchanging data and control messages between adapters to which are attached different users, and a shared memory subsystem comprising a depository storage, a manager of storage and a microprocessor. Such protocol enables the adapters to be the initiators of the transmission and reception of data by using the control lines that connect the manager of storage to all adapters in the same way as the data bus and the address bus. Moreover, the adapters slice the messages into data bursts to which are associated control words specifying the sizes, the owner and the position of the burst in the message. Consequently, those data bursts may be interleaved when transiting on the data bus without the intervention of the microprocessor for the routing, and they will be stored in or read from the depository storage according to the identification of the user in the control word.

Abstract: An object interface is disclosed that supports three modes of inter-object communication--message processing (store and forward), conversational communication, and remote procedure call. A service broker manages service requests from, and responsive services provided by, a plurality of clients and servers, respectively, which may reside on different hardware platforms and operating systems and may be connected to computer networks having different network architectures and associated communications protocols. The broker manages the service offerings from servers and service requests from clients, and clients and servers communicate and exchange information with one another via the broker. The service broker includes different application programming interfaces for allowing participants to access the functionality of the service broker.

Abstract: A hardware mechanism capable of performing state saving and restoring operations, for use in a computer environment having a computer system having a central processor unit (CPU) with one or more data buses, a set of general purpose registers, instruction decoding logic and a mechanism for detecting interrupt conditions. The present invention generates new SAVE and RESTORE control signals and additional memory elements temporarily store the contents of the general purpose registers during interrupt conditions. The hardware mechanism includes an input section for transferring information from the one or more data buses to general purpose registers for storing the information. An output section is used for transferring the stored information from the general purpose registers to the data bus(es).

Abstract: A sequencer chip device, provided for use in a broadband integrated service digital network (B-ISDN), is particularly adapted to control users' traffic at two places in the network: at the user-network interface (UNI) by a traffic enforcer, and at the network-node surface interface (NNI) by a queue manager. The traffic enforcer contains a buffer to delay and reshape violating cells that do not comply with some agreed-upon traffic parameters. The queue manager manages cells in a queue at network nodes in such a way that higher priority cells are always served first, low priority cells are discarded when the queue is full, and any interference between same-priority cells is prevented. Proposed architectures for the traffic enforcer and the queue manager include the chip device. The chip device includes a plurality of modules each of which is divided into three main functional areas: controller, memory and comparator. The chip device is preferably implemented using 1.2 .mu.m CMOS technology.

Abstract: A circuit for use in a peripheral interface unit of a microprocessor-based system that actively drives a tri-state data strobe acknowledge (DSACK*) signal to a logical low state after a delay following assertion of an address strobe by the microprocessor. The DSACK* signal is then actively driven to a logical high state in response to deassertion of the address strobe. The DSACK* signal is then returned to a high impedance state. A Schmitt trigger feedback circuit guarantees that the resulting digital "high" level in the high impedance state will exceed a defined, minimum voltage level, regardless of the circuit's capacitance load.