Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. Upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, a background reference positioning circuit performs background reads of representative pages of each page group of a closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block. When a usage characteristic is determined to meet a usage characteristic threshold, a read circuit performs subsequent host-requested reads using a threshold voltage shift read instruction and reads of pages of the closed block are performed using the set of updated threshold voltage offset values corresponding to the page group of the page being read.

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

Abstract: One controller for controlling operation of a memory device includes an output circuit configured to supply a chip select signal, an address signal, a command signal, and a clock signal to the memory device, and a data processing circuit configured to process read data and write data through a data terminal based on the chip select signal, the address signal, the command signal, and the clock signal supplied by the output circuit. The controller is configured to supply the address signal and the command signal to the memory device a predetermined duration after the output circuit supplies the chip select signal.

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder circuit. The row decoder circuit turns on memory cells of a plurality of cell strings of a selected memory block after applying a first prepulse to a first dummy word line connected to first dummy memory cells after applying a second prepulse to a second dummy word line connected to second dummy memory cells.

Abstract: A logic gate module for performing logic functions including a MRAM cell including a magnetic tunnel junction comprising a sense layer, a storage layer, and a spacer layer. The MRAM cell has a junction resistance determined by the degree of alignment between a sense magnetization of the sense layer and the storage magnetization of the storage layer. The storage magnetization and the sense magnetization are switchable between m directions to store data corresponding to one of m logic states, with m>2, such that the MRAM cell is usable as a n-bit cell with n?2. The logic gate module further includes a comparator for comparing the junction resistance with a reference value and outputting a digital signal indicating a difference between the junction resistance and the reference value, such that logic functions can be performed.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cell groups, the memory cell groups including a first memory group including first memory cells, and a control circuit configured to execute a first write operation targeting the first memory cells in a first mode in which the control circuit executes at least a first programming operation on the first memory cells followed by a multiple number of first verification operations to verify the first programming operation, and then in a second mode, in which the control circuit executes a second programming operation on the first memory cells followed by a second verification operation to verify the second programming operation. A programming voltage applied during the second programming operation is less than a programming voltage applied during the first programming operation, and is adjusted based on a number of first verification operations.

Abstract: A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.

Abstract: The disclosed technology relates generally to non-volatile memory devices, and more particularly to ferroelectric non-volatile memory devices. In one aspect, a non-volatile memory cell includes a pinch-off ferroelectric memory FET and at least one select device electrically connected in series to the pinch-off ferroelectric memory FET.

Abstract: In one embodiment, an integrated circuit comprises a volatile memory including a plurality of memory cells, a detector to detect one or more in-specification conditions, and a discharger, external to the volatile memory, to discharge electric charge stored in the integrated circuit, including electric charge stored in the volatile memory, unless the detector detects the one or more conditions.

Abstract: A booster circuit includes a charge pump circuit and a clock processing circuit. The clock processing circuit includes a first transistor of a first conductivity type, a second transistor of a second conductivity type, and a third transistor of a third conductivity type. The first and second transistors are connected in series between a high-voltage node and a low-voltage node, and gates of the first and second transistors are connected to each other. The third transistor is connected in parallel with the first transistor between the high-voltage node and an output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to the charge pump circuit.

Abstract: A memory device and associated techniques adjust voltage ramping times optimally for each block or sub-block of memory cells to account for fabrication variations. The widths of word lines and select gate lines can vary in different sub-blocks due to misalignments in the fabrication process. The resistance and voltage settling times vary based on the widths. In one aspect, a shortest acceptable ramp down period is determined for a select gate line. This period avoids excessive read errors. A corresponding shortest acceptable word line voltage ramping period is then determined for each sub-block. A pattern in the ramp down periods can be detected among the tested sub-blocks or blocks and used to set ramp down periods in other sub-blocks or blocks. The overall time for a programming or read operation is therefore minimized.

Abstract: A semiconductor storage device includes a memory cell, a switch, a source driver, a drain driver, a voltage measurement circuit and a control electrode driver. The memory cell has a control electrode, a floating electrode, a source and a drain. In a writing to the memory cell, the voltage measurement circuit measures a voltage generated between the control electrode and the source when the switch is in an on state connecting the control electrode and the drain and a predetermined current flows from the current source to the memory cell, and the control electrode driver applies to the control electrode a voltage that is controlled based on the voltage measured by the voltage measurement circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, the cell includes a first capacitor which includes first and second electrodes, and a first transistor which includes first and second terminals and a first control terminal, the first terminal being connected to the first electrode, a first conductive line connected to the second terminal, a second conductive line connected to the second electrode, a sense amplifier, a switch element connected between the first conductive line and the sense amplifier, and a controller turning off the switch element in a write operation, applies a first potential to the first conductive line, and sets a potential of the second conductive line according to a value of write data to be written to the cell.

Abstract: A dynamic NOR circuit includes a pre-charge transistor coupled between a first voltage supply node and a dynamic node to pre-charge the dynamic node. The dynamic NOR circuit includes a first keeper circuit having a first keeper transistor and a second keeper transistor serially coupled between the first voltage supply node and the dynamic node. The dynamic NOR circuit includes a first pull down circuit coupled between the dynamic node and ground. A first input signal is coupled to a gate of a first pull-down transistor in the first pull-down circuit and is also coupled to a gate of the first keeper transistor. A first keeper enable signal is coupled to a gate of the second keeper transistor. Additional keeper circuits and pull down circuits coupled to the dynamic node allow the dynamic NOR structure to handle a plurality of input signals.

Abstract: A memory cell includes a source region and a drain region disposed in a semiconductor body. A channel region is disposed in the semiconductor body between the source region and the drain region. A floating gate is disposed between the semiconductor body and the control gate. The floating gate includes a protruding portion that is located over the channel region between the source and drain regions and spaced therefrom. The protruding portion is separated from the channel region by a first insulating layer that is thinner than a second insulating layer that separates remaining portions of the floating gate from the channel region.

Abstract: According to embodiments of the present invention, a flip-flop circuit is provided. The flip-flop circuit includes a first stage circuit and a second stage circuit, wherein each of the first stage circuit and the second stage circuit is operable in two modes of operation, and a driver arrangement, wherein the first stage circuit includes a first transistor and a first non-volatile memory cell connected to each other, wherein the second stage circuit includes a second transistor and a second non-volatile memory cell connected to each other, and wherein the driver arrangement is configured, at a clock level, to drive the first stage circuit in one of the two modes of operation to access the first non-volatile memory cell and, at the clock level, to drive the second stage circuit in the other of the two modes of operation to access the second non-volatile memory cell.

Abstract: An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical OR between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. The control component can cause storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector.

Abstract: A semiconductor device includes an input clock generation circuit able to shift a write command in synchronization with a clock, and generating first and second input clocks. The semiconductor device also includes a write leveling control circuit able to divide a frequency of the clock in response to a write leveling control signal, and generating first to fourth write clocks. The semiconductor device includes a signal transfer circuit able to transfer the first and second input clocks as first and second transfer clocks in a write operation, and transferring the first to fourth write clocks as first to fourth transfer clocks in a write leveling operation.

Abstract: A method for operating a memory cell structure includes providing a memory cell. An erasing process is performed by applying an erasing voltage to a first gate electrode, a source region and a drain region simultaneously to attract a plurality of electrons from a substrate and to store the plurality of electrons in a first spacer and a second spacer. Afterwards, a programming process is performed by applying a pull-out voltage to the source region or the drain region to remove the plurality of electrons stored in the first spacer or the second spacer, and a read process is performed to determine whether the plurality of electrons is stored in the first spacer and stored in the second spacer.