Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.

Abstract: A circuit includes a first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store a first and a second logic values, respectively. The current sense amplifier is configured to couple the first reference cell to a first node of the current sense amplifier, and couple the second reference cell to a second node of the current sense amplifier for reading bits stored in the first reference cell and the second reference cell.

Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.

Abstract: A nonvolatile memory controller is disclosed that includes a read circuit configured to read memory cells of a nonvolatile memory device and a program and erase circuit configured to program and erase memory cells of the nonvolatile memory device. The nonvolatile memory controller includes a NAND shared algorithm circuit configured to communicate with the nonvolatile memory device so as to enter a test mode of the nonvolatile memory device and configured to modify the trim registers while the nonvolatile memory device is in the test mode such that the nonvolatile memory device performs one or more operations. The operations may include a suspendable program operation, a program suspend operation and an erase suspend operation.

Abstract: One semiconductor device includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal is activated. The latency control circuit activates a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles. The command receiver is activated based on a first control signal. The first control signal is activated in response to the first internal chip select signal. The first control signal is deactivated in response to the second control signal.

Abstract: Systems and methods for low latency acquisition of soft data from a memory cell based on a sensing time and/or a leakage current are described. In one embodiment, the systems and methods may include applying a first read voltage to a word line of a page of memory cells selected by a processor of a flash memory device for a read operation, applying a pass voltage to word lines associated with one or more different pages of memory cells of the memory block, upon applying the first read voltage sensing whether a bit line of a memory cell in the selected page conducts, measuring a side effect associated with sensing whether the bit line of the memory cell in the selected page conducts, and assigning a LLR value to the memory cell as a soft LDPC input based at least in part on the measured side effect.

Abstract: A programmable resistive memory having a plurality of programmable resistive cells. At least one of the programmable resistive cell includes a programmable resistive element and at least one selector. The selector can be built in at least one fin structure and at least one active region divided by at least one MOS gate into a first active region and a second active region. The first active region can have a first type of dopant to provide a first terminal of the selector. The second active region can have a first or a second type of dopant to provide a second terminal of the selector. The MOS gate can provide a third terminal of the selector. The first terminal of the selector can be coupled to the first terminal of the programmable resistive element. The programmable resistive element can be programmed by conducting current flowing through the selector to thereby change the resistance state.

Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

Abstract: A computer-implemented method for performing a voltage-based measurement of a resistive memory cell having a plurality of programmable cell states includes providing, via a processor, a prebiased voltage at a connecting node. The method further includes prebiasing a bitline capacitance of the resistive memory cell. In other aspects, the method includes settling, via the processor, a sensing circuit to a target voltage. The method further includes outputting a resultant value based on a sensed voltage at the resistive memory cell.

Abstract: A booster circuit includes a charge pump circuit and a clock processing circuit. The clock processing circuit includes a first transistor of a first conductivity type, a second transistor of a second conductivity type, and a third transistor of a third conductivity type. The first and second transistors are connected in series between a high-voltage node and a low-voltage node, and gates of the first and second transistors are connected to each other. The third transistor is connected in parallel with the first transistor between the high-voltage node and an output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to the charge pump circuit.

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a write request from a computing host, the write request to specify data to be written to the NAND flash memory; perform a number of program loops to program the data into a plurality of cells of the NAND flash memory, wherein a program loop comprises application of a program voltage to a wordline of the memory to change the threshold voltage of at least one cell of the plurality of cells; and wherein the number of program loops is to be determined prior to receipt of the write request and based on a distribution of threshold voltages of the cells or determined based on tracking a number of program errors for only a portion of the plurality of cells.

Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining usage state information of first memory cells; reading second memory cells by a first read voltage level to obtain at least one first bit and reading the second memory cells by a second read voltage level to obtain at least one second bit according to the usage state information, wherein the first bit corresponds to a storage state of a first part of memory cells among the second memory cells, the second bit corresponds to a storage state of a second part of memory cell among the second memory cells, and the first read voltage level is different from the second read voltage level; and decoding third bits including the first bit and the second bit. Therefore, a decoding efficiency can be improved.

Abstract: Embodiments of the subject invention provide a three transistor, two domain-wall-based magnetic tunnel junction CAM cell (3T-2DW-MTJ CAM). A four transistor, two magnetic tunnel junction ternary CAM cell (4T-2MTJ TCAM) is also provided. An array of the provided CAM cells forms words of various lengths, such as 4-bit, 8-bit, and 16-bit words. Longer CAM words can be formed by an array having hierarchical structures of CAM cells having smaller word sizes, such as 4-bit words or 8-bit words.

Abstract: A nonvolatile memory of an embodiment includes: first through fifth wirings; and a memory cell including: a first circuit including a first magnetoresistive element and a first select transistor, the first magnetoresistive element and the first select transistor being electrically connected in series, the first magnetoresistive element including a first reference layer, a first storage layer, and a first nonmagnetic layer between the first reference layer and the first storage layer; a second circuit including a second magnetoresistive element and a second select transistor, the second magnetoresistive element and the second select transistor being electrically connected in series, the second magnetoresistive element including a second reference layer, a second storage layer, and a second nonmagnetic layer between the second reference layer and the second storage layer; a third circuit including first and second transistors; and a fourth circuit including third and fourth transistors.

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

Abstract: Provided herein are a power-on reset circuit and a semiconductor memory device including the same. The power-on reset circuit may include: a voltage dividing circuit suitable for dividing an external power supply voltage to output a reference voltage, an output node control circuit suitable for controlling a potential level of an output node to an external power supply voltage level or a ground power supply voltage level in response to the reference voltage, and a buffer circuit suitable for buffering the potential level of the output node to output a power-on reset signal. In the voltage dividing circuit, a potential level of the reference voltage in a power up period is different from a potential level of the reference voltage in a power down period.

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract: An extensible configurable FPGA storage structure and an FPGA device, where the FPGA storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.

Abstract: A non-volatile memory system includes one or more control circuits configured to read memory cells. The reading of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with unselected memory cells, allowing the boosting of the channel region for a portion of time while applying the one or more voltages, preventing/interrupting the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, applying a compare signal to the memory cell selected for reading, and performing a sensing operation for the memory cell selected for reading in response to the compare signal.