Abstract: A unipolar photodiode and methods of making and using employ a Schottky contact as a cathode contact. The Schottky cathode contact is created directly on a carrier traveling or collector layer of the unipolar photodiode resulting in a simpler overall structure to use and make. The unipolar photodiode comprises a light absorption layer, the collector layer adjacent to the light absorption layer, the Schottky cathode contact in direct contact with the collector layer, and an anode contact either directly or indirectly interfaced to the light absorption layer. The light absorption layer has a doping concentration that is greater than a doping concentration of the collector layer. The light absorption layer has a band gap energy that is less than that of the collector layer. The light absorption layer and the collector layer may be of the same or opposite conduction type.

Abstract: Excessive CMP (chemical mechanical polishing) of a resistive band region and margin deterioration in processing in a subsequent step are prevented, while a resistive zone is formed with an active region. In the semiconductor device, a source/drain impurity diffusion layer is used as the resistive zone. On a semiconductor substrate, the resistive band region to form the resistive zone, having at least a portion of a surface provided as the active region, is formed. In the resistive band region, the resistive zone is provided. A word line is arranged on the semiconductor substrate so as to surround the resistive zone. In the resistive band region, the area occupancy ratio of the active region per 10 &mgr;m□ is set to be 40% or higher.

Abstract: A field effect transistor includes an n+ high-density impurity injection area, a p+ high-density impurity injection area, an i-impurity non-injection area, and a gate electrode. The gate electrode is free from completely lapping over the i-impurity non-injection area, but laps over substantially half the i-impurity non-injection area adjacent to the n+ high-density impurity injection area so as to avoid channel carrier capture levels due to crystal defects/grain boundaries and an effect of potential barriers due to the channel carrier capture levels.

Abstract: The present invention improves the resolution and accuracy of the presently known two-dimensional position sensing detectors and delivers improved performance in the 1.3 to 1.55 micron wavelength region. The present invention is an array of semiconductor layers with four electrodes, the illustrative embodiment comprising a semi-insulating substrate semiconductor base covered by a semiconductor buffered layer, the buffered layer further covered by a semiconductor absorption layer and the absorption layer covered with a semiconductor layer. Four electrodes are placed on this semiconductor array: two on the top layer parallel to each other and near the ends of opposite edges, and two etched in the buffered layer, parallel to each other and perpendicular to the first set. The layers are doped as to make a p-n junction in the active area. Substantially all the layers, excepting the semi-insulating substrate layer, are uniformly resistive.

Abstract: An electro-optical device includes a TFT, a data line, a scanning line, and a pixel electrode, which are provided above a substrate, a semiconductor layer which constitutes the TFT being connected to the pixel electrode through a relay film. A light-shielding conductive film provided between the data line and the relay film is electrically connected to a capacitor electrode which consists of the same film as the scanning line provided between the relay film and the semiconductor layer at a constant potential, thereby forming a storage capacitor between the films. Therefore, in an electro-optical device of a type in which a light-shielding film against incident light is provided above pixel switching TFT, and a light-shielding film against return light is provided below the TFT, the pixel aperture ratio can be increased, and the storage capacitor can be enlarged.

Abstract: The invention provides a CMOS image sensor that can decrease the influence of the noise charge on the OB cells that determine the darkness level and can prevent the deterioration of the image quality. A region that absorbs the noise charge in a substrate is formed at the periphery of the cell array portion. As in the photodiode, a PN junction is formed in the noise charge absorption region, and one end thereof is connected to a power source voltage. This noise charge absorption region is formed between the cell array portion and the peripheral circuit portion.

Abstract: In a semiconductor light-emitting device, an active layer has a multi quantum well structure (MQW) barrier layers and quantum well layers alternately arranged. Each of the cladding layers has a multi quantum barrier structure (MQB) including barrier layers and well layers alternately arranged. The multi quantum barrier (MQB) of each of the cladding layers varies in a graded or stepwise form. Thus, charge carriers are prevented from overflowing from the active layer, preventing cut-off of a guided wave mode, increasing reflectance of electrons entering the energy barriers, and improving temperature characteristics.

Abstract: The invention is a diode having at least one trench in the semiconductor substrate and insulation configured on the surface of the semiconductor substrate so that the trench limits the depletion region of the diode and the area over which an electrode is in direct contact with the diffusion region of the diode is limited by the insulation. The diode has the advantage that the extent of the depletion region, and thus the area capacitance of the diode, and the size of the electrode are decoupled from one another. The lateral extent of the depletion region can be chosen independently of the size of the electrode.

Abstract: An active pixel sensor for producing images from electron-hole producing radiation includes a crystalline semiconductor substrate having an array of electrically conductive diffusion regions, an interlayer dielectric (ILD) layer formed over the crystalline semiconductor substrate and comprising an array of contact electrodes, and an interconnect structure formed over the ILD layer, wherein the interconnect structure includes at least one layer comprising an array of conductive vias. An array of patterned metal pads is formed over the interconnect structure and are electrically connected to an array of charge collecting pixel electrodes. A radiation absorbing structure includes a photoconductive N-I-B-P photodiode layer formed over the interconnect structure, and a surface electrode layer establishes an electrical field across the radiation absorbing structure and between the surface electrode layer and each of the array of charge collecting pixel electrodes.

Abstract: The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying out dry etching using a fluorine-based gas with a photoresist 17a used as a mask, an auxiliary mask 15a is formed by patterning the insulation membrane. Next, by carrying out dry etching using a chlorine-based gas using the auxiliary mask 15a and the remaining photoresist 17a as masks, wiring 13a is formed by patterning the wiring layer 13. In the second etching, the auxiliary mask 15a is scarcely etched. Therefore, if the thickness of the photoresist 17a is equivalent to that in the prior arts, it is possible to pattern a thicker wiring layer 13 than in the prior arts.

Abstract: Disposing the light absorption layer formed in contact with a polycrystal silicon layer of a bottom gate type polycrystal silicon TFT allows a depletion layer formed between drain and channel forming regions to extend further into the inside of the light absorption layer, resulting in collection of photo carriers produced in the depletion layer into the channel forming region. The photo carriers collected into the channel forming region are subsequently collected into the source region to be output as large photocurrents by high mobility of the polycrystal silicon.

Abstract: An opto-electronic device configured as a photodetector has a capacitor and/or resistor monolithically formed on a surface of the photodetector. The capacitor capacitively couples the AC ground of the photodetector to the bias terminal of the photodetector. The on chip capacitor design eliminates the inductance of external circuit traces between the power supply and an external capacitor. The resistor forces the AC return current of the photodetector through the AC ground in preference to the typical (DC bias terminal) path. Combinations of capacitors and resistors are particularly effective in reducing crosstalk among adjacent detectors in arrays.

Abstract: A chip package includes a chip having a first surface provided with a first terminal and a second surface provided with at least one second terminal, the second surface being opposite to the first surface, a first conductive layer formed on the first surface of the chip, a second conductive layer formed on the second surface of the chip, and a substrate attached to the second surface of the chip and including at least one conductive via hole connected to the second terminal of the chip. And the present invention provides a chip package assembly including the chip package. Further, a method of manufacturing the chip package and an assembly including the chip package are provided. The chip package does not use a bonding wire and additional conductive lands, thereby reducing the size of the package and simplifying the manufacturing process.

Abstract: The solid-state imaging device according to one embodiment of the present invention includes a semiconductor substrate, a plurality of photoelectric conversion regions arrayed in the vertical direction and the horizontal direction on the surface of the substrate, and an electric charge transfer region disposed between the photoelectric conversion regions adjacent in the horizontal direction of the substrate. The substrate comprises a n-type semiconductor substrate, a first p-type impurity region formed on the n-type semiconductor substrate, a semiconductor regions formed on the first p-type impurity region, and a second p-type impurity region disposed below the electric charge transfer region. The photoelectric conversion region and the electric charge transfer region are n-type impurity regions formed on the surface portion of the semiconductor region.

Abstract: In a semiconductor device of the present invention, a first semiconductor region is formed so that a peripheral edge thereof is located between a first field plate ring that corresponds to one of field plate rings located at the innermost side thereof and a second field plate ring that corresponds to one of the field plate rings adjacent the first plate ring. Accordingly, when a surge voltage is applied to the semiconductor device of the present invention, an electric field concentration at a part of the isolation film located under the first one of the field plate rings is relaxed and an electric field intensity decreases. Therefore, the reliability of the isolation film for withstanding the surge voltage increases.

Abstract: A programmable memory transistor (PMT) comprising an IGFET and a coupling capacitor in a semiconductor substrate. The IGFET comprises source and drain regions, a channel therebetween, a gate insulator overlying the channel, and a first floating gate over the gate insulator. The capacitor comprises a lightly-doped well of a first conductivity type, heavily-doped contact and injecting diffusions of opposite conductivity types in the lightly-doped well, a control gate insulator overlying a surface region of the lightly-doped well between the contact and injecting diffusions, a second floating gate on the control gate insulator, and a conductor contacting the lightly-doped well through the contact and injecting diffusions. The first and second floating gates are preferably patterned from a single polysilicon layer, such that the second floating gate is capacitively coupled to the lightly-doped well, and the latter defines a control gate for the first floating gate.

Abstract: An object of the present invention is to provide an EL display device having a high operation performance and reliability. The switching TFT 201 formed within a pixel has a multi-gate structure, which is a structure which imposes an importance on reduction of OFF current value. Further, the current control TFT 202 has a channel width wider than that of the switching TFT to make a structure appropriate for flowing electric current. Morever, the LDD region 33 of the current control TFT 202 is formed so as to overlap a portion of the gate electrode 35 to make a structure which imposes importance on prevention of hot carrier injection and reduction of OFF current value.

Abstract: The present invention relates to a complementary metal-oxide semiconductor (CMOS) image sensor. Particularly, the present invention provides effects of suppressing electrical and optical interferences and improving light sensitivity in a unit pixel of a highly integrated and low power consuming CMOS image sensor. In order to achieve these effects, a red pixel is two-dimensionally encompassed by a green pixel and a blue pixel formed with an additional p-type ion implantation region for suppressing the interference between the pixels. Also, in addition to the above-described structure, a photodiode optimized to the blue pixel is formed further to enhance the light sensitivity.

Abstract: A transistor with ballast resistor formed between the transistor drain and the drain contact is formed by masking regions of the ballast resistor to increase resistivity and thus reduce required area. The invention achieves this without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size for the same ESD requirement or allows better ESD protection for a given die size.

Abstract: An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact between the floating diffusion region and the gate of a source follower output transistor. The buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a buried contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.