Abstract: The ROM device has a memory array including memory cells formed by an access element and a data storage element; a high voltage column decoder stage; a high voltage row decoder stage; an analog stage; and a writing stage, wherein the data storage elements are electrically non-programmable and non-modifiable. The memory array is formed by memory cells having a first logic state and by memory cells having a second logic state. The data storage element of the memory cells having the first logic state is formed by a continuous conductive path uninterruptedly connecting the access transistor to the respective bit line, the data storage element of the memory cells having the second logic state is formed by a region of dielectric material insulating the access transistor from the respective bit line.

Abstract: A processing device determines difference error counts for a difference error that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory component. A processing device scales each of the plurality of difference error counts by a respective scale factor of the scale factors. The processing device adjusts the valley margins of the memory cell in accordance with the scaled difference error counts.

Abstract: A random code generator includes a control circuit, a high voltage power supply, a memory module and a counter. The control circuit generates a control signal and an enabling signal. During a program cycle, the enabling signal is activated. The high voltage power supply receives the enabling signal. A charge pump of the high voltage power supply generates a program voltage according to an oscillation signal. When the enabling signal is activated, the high voltage power supply outputs the program voltage. The memory module determines a selected memory cell of the memory module according to the control signal. During the program cycle, the selected memory cell receives the program voltage. During the program cycle, the counter counts a pulse number of the oscillation signal to acquire a counting value, and the control circuit determines a random code according to the counting value.

Abstract: A non-volatile memory device driving method, applicable to a non-volatile memory device comprising a row decoder and a memory array, comprises: utilizing the row decoder to transmit multiple word line signals to multiple word lines of the memory array; according to an address, utilizing the row decoder to switch a selected word line signal of the multiple word line signals from a predetermined voltage level to a program voltage level; utilizing the row decoder to switch at least one support word line signal of the multiple word line signals from the predetermined voltage level to a first pass voltage level; when the selected word line signal is remained at the program voltage level, utilizing the row decoder to switch the at least one support word line signal from the first pass voltage level to a higher second pass voltage level.

Abstract: A memory includes a memory array, multiple match lines and multiple sets of search lines. The memory array includes multiple memory cells. Each memory cell includes an output terminal, two rectifier elements and two resistor elements. The two resistor elements are configured to store two bits representing a data status. The match lines are coupled to output terminals of the memory cells respectively. Each set of search lines includes a first search line and a second search line. A first resistor element and a first rectifier element of the same memory cell are connected in series between the first search line of the same set of search lines and the output terminal. A second resistor element and a second rectifier element of the same memory cell are connected in series between the second search line of the same set of search lines and the output terminal.

Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

Abstract: A system for generating random noise includes a nanoscale magnetic device with two free ferromagnetic layers separated by a non-magnetic spacer layer. A current source directs a high current perpendicularly through the layers. The magnetic moments of the two free layers are excited by the spin transfer torque (STT) effect and continuously switch from a first direction to a second direction substantially antiparallel to said first direction with random transitions. The device output signal is a series of pulses with voltage peaks with random transition times between the peaks. The device output signal is input to a clipping circuit that cuts the signal off at certain voltage levels. A clocking circuit can sample the output of the clipping circuit to generate a random number.

Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.

Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

Abstract: An example apparatus includes a memory device having first sensing circuitry positioned adjacent an edge of an edge array section and selectably coupled to a row memory cells, the first sensing circuitry including a first sense amplifier selectably coupled via a first sense line to a first memory cell in the row and via a second sense line to the first memory cell. The example apparatus includes second sensing circuitry positioned at an opposite edge of the edge array section and selectably coupled to the row via a third sense line, the second sensing circuitry including a second sense amplifier selectably coupled via the third sense line to a second memory cell in the row. The example apparatus further includes a component positioned outside the edge array section and proximate the first sensing circuitry, the component configured to perform an operation based on data sensed by the first sensing circuitry.

Abstract: A nonvolatile semiconductor storage device includes a plurality of cell transistor pairs including a pair of cell transistors sharing a first node connected to a bit line or a source line, and a dummy gate line laid in parallel with gate lines of the cell transistors, the dummy gate line applying an off voltage to a dummy transistor between the cell transistor pairs. The gate lines and the dummy gate line may be laid at equal intervals. A plurality of impurity diffusion layers corresponding to the first node and second nodes of the cell transistors may be formed at equal intervals in a continuous active region.

Abstract: An operating method of a non-volatile memory device including a plurality of memory cells respectively connected to a plurality of word lines is provided. The operating method includes applying an erase detect voltage to a selected word line of the plurality of word lines to perform an erase detect operation on memory cells connected to the selected word line in response to a program command, applying a program voltage to the selected word line after the erase detect operation, and counting a number of undererased cells of the memory cells on which the erase detect operation has been performed.

Abstract: The various implementations described herein include magnetic memory devices and systems, and methods for injecting defects into the devices and systems. In one aspect, a magnetic memory device comprises a non-magnetic cylindrical core, a first portion, and a second portion. The core is configured to receive a current. The first portion surrounds the core and is configured to introduce magnetic instabilities into the second portion. The second portion is adjacent to and arranged in a stack with respect to the first portion. The second portion also surrounds the core and is configured to store information based on a respective position of the magnetic instabilities. The second portion comprises a first plurality of magnetic layers and a first plurality of non-magnetic layers. Respective magnetic layers of the first plurality of magnetic layers are separated by respective non-magnetic layers of the plurality of non-magnetic layers.

Abstract: According to one embodiment, a memory system includes first, second, and third ICs. The first IC includes a non-volatile semiconductor memory. The second IC includes a controller configured to control the non-volatile semiconductor memory. The third IC is configured to receive an external first power supply voltage and generate a second power supply voltage. The third IC is connected to the second IC via an interface according to a serial communication standard. A temperature sensor element is connected to the third IC.

Abstract: The present disclosure relates to a data out buffer and a memory device having the same. The data out buffer includes a pull-up main driver, coupled between a power supply terminal and an output terminal, configured to output data of a high level; and a pull-down main driver, coupled between the output terminal and a ground terminal, configured to output data of a low level, wherein the pull-up main driver comprises a main pull-up transistor of a first type; and a plurality of first trim transistors, each of a second type.

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract: The present disclosure is directed to a spin current magnetization rotational element, a spin-orbit-torque magnetoresistance effect element, a magnetic memory, and a high-frequency magnetic element which can efficiently generate a pure spin current and reduce a reversal current density. The spin current magnetization rotational element includes: a spin-orbit torque wiring extending in a first direction; and a first ferromagnetic layer laminated in a second direction which intersects the first direction, wherein the spin-orbit torque wiring includes at least one rare gas element of Ar, Kr, and Xe.

Abstract: Aspects of the present disclosure are directed to generating endurance measures for a memory sub-system and using endurance measures to classify memory sub-systems, to predict memory system remaining life, and to create memory systems with consistently performing sub-systems. An endurance measure can be generated by computing multiple metric points. Each metric point can be based on a margin between a point, in cumulative distribution function (CDF)-based data at an acceptable memory unit failure rate, and an error amount threshold condition. Once a there are sufficient metric points related to the memory device, the metric points can be fit to a function. The endurance measure is then obtained by extrapolating the function to a point at which the function reaches a threshold.