Patents Examined by Geoffrey Ida
-
Patent number: 8471314Abstract: A solid-state imaging device includes a substrate having a first surface and a second surface, light being incident on the second surface side; a wiring layer disposed on the first surface side; a photodetector formed in the substrate and including a first region of a first conductivity type; a transfer gate disposed on the first surface of the substrate and adjacent to the photodetector, the transfer gate transferring a signal charge accumulated in the photodetector; and at least one control gate disposed on the first surface of the substrate and superposed on the photodetector, the control gate controlling the potential of the photodetector in the vicinity of the first surface.Type: GrantFiled: February 11, 2010Date of Patent: June 25, 2013Assignee: Sony CorporationInventors: Yasushi Maruyama, Tetsuji Yamaguchi, Takashi Ando, Susumu Hiyama, Yuko Ohgishi
-
Patent number: 8426838Abstract: A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact.Type: GrantFiled: November 27, 2008Date of Patent: April 23, 2013Assignee: Higgs Opl. Capital LLCInventor: Frederick T Chen
-
Patent number: 8378423Abstract: A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each other, a second dielectric layer covering the first and second electrodes, and a second gate formed on the second dielectric layer, in which at least one of the first and second gates is non-overlapped with the second electrode.Type: GrantFiled: March 24, 2011Date of Patent: February 19, 2013Assignee: AU Optronics Corp.Inventors: Chung-Yu Liang, Feng-Yuan Gan, Ting-Chang Chang
-
Patent number: 8344423Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.Type: GrantFiled: January 27, 2012Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Yasuhiro Uemoto, Masahiro Hikita, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda
-
Patent number: 8309963Abstract: The invention is an organic luminescence transistor device including: a substrate; an assistance electrode layer provided on a side of an upper surface of the substrate; an insulation film provided on a side of an upper surface of the assistance electrode layer; a first electrode provided locally on a side of an upper surface of the insulation film, the first electrode covering an area of a predetermined size; an electric-charge-injection inhibiting layer provided on an upper surface of the first electrode, the electric-charge-injection inhibiting layer having a shape larger than that of the first electrode in a plan view; an electric-charge injection layer provided on the side of an upper surface of the insulation film at an area not provided with the first electrode or the electric-charge-injection inhibiting layer and on an upper surface of the electric-charge-injection inhibiting layer; a luminescent layer provided on an upper surface of the electric-charge injection layer; and a second electrode layer prType: GrantFiled: February 26, 2010Date of Patent: November 13, 2012Assignee: Dai Nippon Printing Co., Ltd.Inventors: Katsunari Obata, Shinichi Handa, Takuya Hata, Kenji Nakamura, Atsushi Yoshizawa, Hiroyuki Endo
-
Patent number: 8283251Abstract: A method for manufacturing a wafer level package including: forming a redistribution line connected to a top surface of a die pad on a wafer with the die pad; additionally preparing a carrier film including a metal post with a concave central portion on one surface; bonding the metal post to a top surface of the redistribution line; molding a space between the metal posts with a molding resin; and removing the carrier film.Type: GrantFiled: September 22, 2011Date of Patent: October 9, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Seoup Lee, Sung Yi
-
Patent number: 8273648Abstract: Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof.Type: GrantFiled: February 9, 2012Date of Patent: September 25, 2012Assignee: International Business Machines CorporationInventors: Choongyeun Cho, Daeik Kim, Jonghae Kim, Moon Ju Kim, James R. Moulic
-
Patent number: 8253240Abstract: A cap member capable of alleviating degradation of reliability and improving fabrication yields is provided. The cap member has a cylindrical side wall portion, a top face portion closing one end of the side wall portion and having a light exit hole formed therein to allow extraction of laser light from a semiconductor laser chip; a light transmission window fitted to the top face portion to stop the light exit hole, and a flange portion arranged at the other end of the side wall portion and welded on the upper face of a stem on which the semiconductor laser chip is mounted. A groove portion is formed in an inner surface of the top face portion, and this groove portion makes part of the top face portion in a predetermined region less thick than the other part thereof.Type: GrantFiled: November 24, 2008Date of Patent: August 28, 2012Assignee: Sharp Kabushiki KaishaInventors: Masaya Ishida, Daisuke Hanaoka, Takeshi Horiguchi
-
Patent number: 8232656Abstract: Wire bonding method for reducing height of a wire loop in a semiconductor device, including a first bonding step of bonding an initial ball formed at a tip end of a wire onto a first bonding point using a capillary, thereby forming a pressure-bonded ball; a wire pushing step of pushing the wire obliquely downward toward the second bonding point at a plurality of positions by repeating a sequential movement for a plurality of times, the sequential movement including moving of the capillary substantially vertically upward and then obliquely downward toward the second bonding point by a distance shorter than a rising distance that the capillary has moved upward; and a second bonding step of moving the capillary upward and then toward the second bonding point, and bonding the wire onto the second bonding point by pressure-bonding.Type: GrantFiled: October 20, 2010Date of Patent: July 31, 2012Assignee: Kabushiki Kaisha ShinkawaInventors: Tatsunari Mii, Shinsuke Tei, Hayato Kiuchi
-
Patent number: 8231333Abstract: A fan unit has a fan (10). Associated with the fan is an air-guiding tube (22) through which the fan (10) transports air, during operation. The air-guiding tube (22) is connected to at least one carrier tube (23) for suspension of the fan (10). The fan includes a carrier part (25). A damping member (30) is arranged between the carrier part (25) and the carrier tube (23) to reduce any structure-borne sound which occurs during operation of the fan (10).Type: GrantFiled: February 9, 2009Date of Patent: July 31, 2012Assignee: EBM-Papst St. Georgen GmbH & Co. KGInventor: Peter Ragg
-
Patent number: 8207521Abstract: Disclosed herein is a method for producing catalyst-free single crystal silicon nanowires. According to the method, nanowires can be produced in a simple and economical manner without the use of any metal catalyst. In addition, impurities contained in a metal catalyst can be prevented from being introduced into the nanowires, contributing to an improvement in the electrical and optical properties of the nanowires. Also disclosed herein are nanowires produced by the method and nanodevice comprising the nanowires.Type: GrantFiled: February 18, 2010Date of Patent: June 26, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Eun Kyung Lee, Dongmok Whang, Byoung Lyong Choi, Byung Sung Kim
-
Patent number: 8183603Abstract: A solid-state imaging device includes a substrate having a first surface and a second surface, light being incident on the second surface side; a wiring layer disposed on the first surface side; a photodetector formed in the substrate and including a first region of a first conductivity type; a transfer gate disposed on the first surface of the substrate and adjacent to the photodetector, the transfer gate transferring a signal charge accumulated in the photodetector; and at least one control gate disposed on the first surface of the substrate and superposed on the photodetector, the control gate controlling the potential of the photodetector in the vicinity of the first surface.Type: GrantFiled: February 22, 2007Date of Patent: May 22, 2012Assignee: Sony CorporationInventors: Tetsuji Yamaguchi, Yasushi Maruyama, Takashi Ando, Susumu Hiyama, Yuko Ohgishi
-
Patent number: 8174073Abstract: A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET includes a second fin spaced apart from the first fin by a fin space; and a second gate electrode over a top surface and sidewalls of the second fin. The second gate electrode is electrically disconnected from the first gate electrode. The first and the second gate electrodes have a gate height greater than about one half of the fin space.Type: GrantFiled: May 30, 2007Date of Patent: May 8, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Lin Lee, Chang-Yun Chang, Sheng-Da Liu, Fu-Liang Yang
-
Patent number: 8168454Abstract: Provided is a vertical LED including an n-electrode; an n-type GaN layer formed under the n-electrode, the n-type GaN layer having a surface coming in contact with the n-electrode, the surface having a Ga+N layer containing a larger amount of Ga than that of N; an active layer formed under the n-type GaN layer; a p-type GaN layer formed under the active layer; a p-electrode formed under the p-type GaN layer; and a structure support layer formed under the p-electrode.Type: GrantFiled: May 14, 2009Date of Patent: May 1, 2012Assignee: Samsung LED Co., Ltd.Inventors: Su Yeol Lee, Sang Ho Yoon, Doo Go Baik, Seok Beom Choi, Tae Sung Jang, Jong Gun Woo
-
Patent number: 8169031Abstract: A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy can be derived from either a semiconductor nanowire or an epitaxial grown semiconductor material. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion. The lower portion of the continuous metal semiconductor alloy and the vertical pillar portion are not separated by a material interface. Instead, the two portions of the continuous metal semiconductor alloy are of unitary construction, i.e.Type: GrantFiled: August 26, 2008Date of Patent: May 1, 2012Assignee: International Business Machines CorporationInventors: Guy M. Cohen, Christos D. Dimitrakopoulos, Alfred Grill
-
Patent number: 8163627Abstract: A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area; forming a first insulating layer for filling a lower portion of the trench; forming a porous second insulating layer on the first insulating layer for filling a space between the charge storage layers; forming a third insulating layer on a side wall of the trench and the second insulating layer, the third insulating layer having a density higher than that of the second insulating layer; and forming a porous fourth insulating layer for filling the trench.Type: GrantFiled: December 13, 2007Date of Patent: April 24, 2012Assignee: Hynix Semiconductor Inc.Inventors: Jung Geun Kim, Eun Soo Kim, Seung Hee Hong, Suk Joong Kim
-
Patent number: 8158970Abstract: The invention is an organic luminescence transistor device including: a substrate; an assistance electrode layer provided on a side of an upper surface of the substrate; an insulation film provided on a side of an upper surface of the assistance electrode layer; a first electrode provided locally on a side of an upper surface of the insulation film, the first electrode covering an area of a predetermined size; an electric-charge-injection inhibiting layer provided on an upper surface of the first electrode, the electric-charge-injection inhibiting layer having a shape larger than that of the first electrode in a plan view; an electric-charge injection layer provided on the side of an upper surface of the insulation film at an area not provided with the first electrode or the electric-charge-injection inhibiting layer and on an upper surface of the electric-charge-injection inhibiting layer; a luminescent layer provided on an upper surface of the electric-charge injection layer; and a second electrode layer prType: GrantFiled: December 1, 2006Date of Patent: April 17, 2012Assignee: Dai Nippon Printing Co., Ltd.Inventors: Katsunari Obata, Shinichi Handa, Takuya Hata, Kenji Nakamura, Atsushi Yoshizawa, Hiroyuki Endo
-
Patent number: 8143155Abstract: After forming a pressure-bonded ball and a ball neck by bonding an initial ball to a pad, a capillary is moved upward, away from a lead, and then downward, thereby the ball neck is trodden on by a face portion that is on the lead side of the capillary. Subsequently, the capillary is moved upward and then toward the lead until the face portion of the capillary is positioned above the ball neck, thereby a wire is folded back toward the lead. Then, the capillary is moved downward such that a side of the wire is pressed by the capillary against the ball neck that has been trodden on. After the capillary is moved obliquely upward toward the lead and then looped toward the lead, the wire is pressure-bonded to the lead.Type: GrantFiled: October 21, 2009Date of Patent: March 27, 2012Assignee: Kabushiki Kaisha ShinkawaInventors: Tatsunari Mii, Shinsuke Tei, Hayato Kiuchi
-
Patent number: 8137056Abstract: An impingement cooled structure includes a plurality of shroud members disposed in a circumferential direction to constitute a ring-shaped shroud surrounding a hot gas stream, and a shroud cover mounted on radial outside faces of the shroud members to form a cavity therebetween. The shroud cover has a first impingement cooling hole which communicates with the cavity and allows cooling air to be jetted to an inside thereof so as to cool an inner surface of the cavity by impingement. The shroud members each has a hole fin. The hole fin divides the cavity into a plurality of sub-cavities. Further, the hole fin has a second impingement cooling hole which allows the cooling air having flowed through the first impingement cooling hole to be jetted obliquely toward a bottom surface of the sub-cavity adjacent thereto.Type: GrantFiled: February 26, 2007Date of Patent: March 20, 2012Assignees: IHI Corporation, Japan Aerospace Exploration AgencyInventors: Shu Fujimoto, Youji Ohkita, Yoshitaka Fukuyama, Takashi Yamane, Masahiro Matsushita, Toyoaki Yoshida
-
Patent number: 8138615Abstract: A semiconductor integrated circuit relating to one aspect of the present invention includes a power transistor, at least one or more of first metal patterns functioning as a first electrode of the power transistor and at least one or more of second metal patterns functioning as a second electrode of the power transistor formed in an interlayer insulation film on the transistor, at least one or more of first busses electrically connected to a corresponding first metal pattern of the at least one or more of the first metal patterns, a single second bus electrically connected to the at least one or more of second metal patterns, and a contact pad provided to each of the at least one or more of first busses and the single second bus.Type: GrantFiled: November 28, 2007Date of Patent: March 20, 2012Assignee: Panasonic CorporationInventors: Shingo Fukamizu, Yutaka Nabeshima, Yasunori Yamamoto