Abstract: Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.

Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

Abstract: In order to reliably remove, by wet etching, a compound containing a metal and silicon, e.g., a silicate (101a) containing hafnium metal, the silicate (101a) is oxidized and then the oxidized silicate (101a) is wet-etched.

Abstract: A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features therein in spaced relation to each other which define an opening therebetween. A blanket polysilicon is formed over the wafer assembly and within the opening. A patterned photoresist layer is formed over the polysilicon layer, then the polysilicon layer within the opening is etched with a first etch. Subsequent to the first etch, the polysilicon with the opening is etched with a second etch comprising a halogen-containing gas flow rate of from about 35 sccm to about 65 sccm and an oxygen-containing gas (for example He—O2) flow rate of from about 12 sccm to about 15.6 sccm.

Abstract: The present invention relates to a method for fabricating a semiconductor device. In more detail of the aforementioned method, a first mask layer covering a cell region is formed on an insulation layer in the cell region. Meanwhile, a second mask layer is formed in a peripheral circuit region with a predetermined distance from the first mask layer. The insulation layer is then etched with use of the first and the second mask layers as an etch mask to form a spacer at both sidewalls of each gate line pattern in the peripheral region and simultaneously form a guard beneath the second mask layer. The first and the second mask layers are removed thereafter. Next, a third mask layer opening the cell region but covering the whole regions including a guard region in the peripheral circuit region is formed. A wet etching process is performed to the insulation layer remaining in the cell region by using the third mask layer as an etch mask.

Abstract: A method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits includes the following steps: providing a substrate; providing a whisker-containing layer made of aluminum metal or an aluminum alloy on the substrate; back-etching and/or resputtering the whisker-containing layer such that the whiskers are essentially removed; and structuring the whisker-free layer into the lines.

Abstract: Methods and systems for preparing a substrate for analysis are provided. One method includes removing a portion of a copper structure on the substrate using an etch chemistry in combination with an electron beam. The etch chemistry is substantially inert with respect to the copper structure except in the presence of the electron beam. Other methods involve forming masking layers on a substrate that will protect the substrate during etching. For example, one method includes exposing a first portion of the substrate to an electron beam. A second portion of the substrate not exposed to the electron beam includes a copper structure. The method also includes exposing the substrate to a fluorine containing chemical. The fluorine containing chemical bonds to the first portion but not the second portion to form a fluorine containing layer on the first portion.

Abstract: In accordance with the foregoing objects and advantages, the present invention provides a fabrication device that may be used during the grinding operation of the fabrication process. The fabrication device comprises a socket plate that includes a plurality of cavities formed therein that correspond in position and number to the solder (or other conductive material) bumps formed on the front surface of a product wafer.

Abstract: In the control method in a management system of semiconductor manufacturing equipment to enhance a product yield through a control of etching process, information of a corresponding lot for the etching process is recognized. It is checked whether the information of corresponding lot is for an etching process after a predetermined RF time of etching apparatus. RF time of the etching apparatus is compared with the predetermined RF time, and it is decided whether the etching process of corresponding lot can be performed in the etching apparatus if the etching process for the corresponding lot should be performed after a lapse of the predetermined RF time.

Abstract: Antimony-based semiconductor devices are formed over a substrate structure (10) that includes an antimony-based buffer layer (24) and an antimony-based buffer cap (26). Multiple epitaxial layers (30–42) formed over the substrate structure (10) are dry etched to form device mesas (12) and the buffer cap (26) provides a desirably smooth mesa floor and electrical isolation around the mesas.

Abstract: A tungsten CMP solution for planarizing semiconductor wafers includes a primary oxidizer having a sufficient oxidation potential for oxidizing tungsten metal to tungsten oxide; and the tungsten CMP solution has a static etch rate for removing the tungsten metal. A secondary oxidizer lowers the static etch rate of the tungsten CMP solution. The secondary oxidizer is selected from the group consisting of bromates and chlorates. Optionally the tungsten CMP contains 0 to 50 weight percent abrasive particles; and it contains a balance of water and incidental impurities.

Abstract: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped.

Abstract: According to one embodiment a method is disclosed. The method includes applying a photoresist layer to a first wafer, etching the first wafer, bonding the first wafer to a second wafer and thinning the first wafer; wherein an unsupported bevel portion of the first wafer is removed.

Abstract: An etching processing method capable of etching a low dielectric constant layer at a reduced cost by using an etching processing apparatus comprising a vacuum vessel, a sample loading electrode disposed in the vacuum vessel, a gas introduction device for introducing a reaction gas into the vacuum vessel, an antenna for forming plasmas in the vacuum vessel, and a high frequency power supply for supplying a bias power to a sample loaded on the sample loading electrode, wherein the bias power to be supplied to the sample is 3 W/cm2 or less, and the gas introduction device introduces a gas containing chlorine atoms or bromine atoms to apply etching processing to an inorganic insulation material of low dielectric constant loaded on the loading electrode.

Abstract: An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.

Abstract: A process for treating a copper or copper alloy substrate surface with a composition and corrosion inhibitor solution to minimize defect formation and surface corrosion, the method including applying a composition including one or more chelating agents, a pH adjusting agent to produce a pH between about 3 and about 11, and deionized water, and then applying a corrosion inhibitor solution. The composition may further comprise a reducing agent and/or corrosion inhibitor. The method may further comprise applying the corrosion inhibitor solution prior to treating the substrate surface with the composition.

Abstract: A method for peeling off a thin film semiconductor element over an insulating surface by using a void, and a method for manufacturing a semiconductor device by transferring the peeled semiconductor element. According to the peeling method of the invention, a first base layer having a plurality of recessed portions is formed over a substrate, and a second base layer having a plurality of voids is formed on the recessed portions of the first base layer. On the second base layer, a third base layer is formed and a semiconductor element is formed thereon. Then, by separating the second base layer at an intersecting surface with the voids, the semiconductor element is peeled off from the substrate.

Abstract: A method of patterning a layer of magnetic material to form isolated magnetic regions. The method forms a mask on a film stack comprising a layer of magnetic material such that the protected and unprotected regions are defined. The unprotected regions are etched in a high temperature environment to form isolated magnetic regions.

Abstract: A method of reducing a critical dimension (“CD”) bias between a dense pattern and an isolation pattern is disclosed. The method includes a first step of providing a mask having a dense pattern, an isolation pattern and the other area of the mask is transparent, in which mask the dense pattern has a first opaque pattern and the isolation pattern has a second opaque pattern. The second step of the method is forming a virtual pattern around the isolation pattern, in which a distance between the virtual pattern and the isolation pattern is y, and the virtual pattern has a pattern line width x. By forming the virtual pattern around the isolation pattern, the flare effect of the isolation pattern is close to that of the dense pattern, thus the CD bias between a dense pattern, and an isolation pattern is reduced, and the process window does not shrink.

Abstract: A method for forming a trench in a semiconductor silicon substrate. An anti-reflective coating layer and a photoresist layer are formed over the substrate and patterned in accordance with a location for the trench. During the trench etch into the silicon substrate, the etch environment is monitored to detect the material of the anti-reflective coating layer. The etch process is controlled in response to detecting the removal of this material and the known etch rate differential between the anti-reflective coating material layer and the silicon substrate.