Abstract: An apparatus can include first circuitry coupled to a FIFO memory. The first circuitry can provide a write pointer of the FIFO memory at a first rate. Second circuitry can be coupled to the FIFO memory. The second circuitry can provide a read pointer of the FIFO memory at a second rate that is different from the first rate. Third circuitry can be coupled to the first and second circuitries. The third circuitry can provide an indication of an error condition of the FIFO memory based on the write pointer and the read pointer.

Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

Abstract: Methods and systems are disclosed for cross-chiplet performance data streaming. Techniques disclosed include accumulating, by a subservient chiplet, event data associated with an event indicative of a performance aspect of the subservient chiplet; sending, by the subservient chiplet, the event data over a chiplet bus to a master chiplet; and adding, by the master chiplet, the received event data to an event record, the event record containing previously received, from the subservient chiplet over the chiplet bus, event data associated with the event.

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.

Abstract: A neural processing unit includes an internal memory including a plurality of memory units; a controller configured to control read and write operations of data in at least one of an input feature map domain, a weight domain, and an output feature map domain with respect to each of the plurality of memory units based on an operation schedule in a machine code in which a plurality of operation steps of an artificial neural network model are set.

Abstract: In example implementations, an apparatus is provided. The apparatus includes a riser card body, a first interface, a first 2×8 slot on a surface of the riser card body, and a second 2×8 slot on a same side of the surface of the riser card body as the first 2×8 slot. The first interface includes a first set of fingers and a second set of fingers at an end of the riser card body to connect to a peripheral component interconnect express (PCIe) slot of a motherboard. The first 2×8 slot and the second 2×8 slot are positioned perpendicular to the PCIe slot of the motherboard.

Abstract: In one example, an apparatus comprises: a direct memory access (DMA) descriptor queue that stores DMA descriptors, each DMA descriptor including an indirect address; an address translation table that stores an address mapping between indirect addresses and physical addresses; and a DMA engine configured to: fetch a DMA descriptor from the DMA descriptor queue to the address translation table to translate a first indirect address of the DMA descriptor to a first physical address based on the address mapping, and perform a DMA operation based on executing the DMA descriptor to transfer data to or from the first physical address.

Abstract: An electronic device includes a memory and a processor. The processor receives a platform management profile that includes information defining one or more platform management policies, a given platform management policy among the one or more platform management policies including a provided input from a specified hardware or software sensor and/or a provided output action. The processor uses the given platform management policy for controlling operating states of elements in the electronic device.

Abstract: A method and system for detecting performance regression in a software application is disclosed. The software application comprises a feature flag having at least two states, wherein in a first state a first version of a feature is provided and in a second state a second version of the feature is provided when the software application is executed. The feature flag is further wrapped in a timer for recording the time taken for the corresponding first and second versions of the feature to be provided.

Abstract: Disclosed are a medical device and a data management method therefor. The data management method includes: receiving an instruction for selecting a locking rule to determine a target locking rule, wherein the target locking rule is used for screening monitoring data so as to carry out locking; under the trigger of a first trigger condition, screening the monitoring data according to the target locking rule, and locking the screened monitoring data; and under the trigger of a second trigger condition, selectively deleting monitoring data that is not locked. An operator can selectively lock the monitoring data by selecting the locking rule, thereby avoiding the deletion of monitoring data needing to be retained, and facilitating the management of the monitoring data.

Abstract: A communication interface buffer comprises: a data bus connection adapted to be coupled to a bus interface contact; and a ground. The communication interface buffer also comprises an output transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal coupled to the data bus connection, the second current terminal coupled to ground, and the control terminal adapted to receive a drive signal. The communication interface buffer also comprises a control circuit coupled to the control terminal of the output transistor, wherein the control circuit is configured to: turn off the output transistor during a first interval that starts when the data bus connection is coupled to the bus interface contact; and turn on the output transistor after the first interval is complete.

Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.

Abstract: A storage device includes a nonvolatile memory device and a controller that accesses the nonvolatile memory device based on a request of an external host device, receives a first clock signal from the external host device, generates a second clock signal through frequency multiplication of the first clock signal, and communicates with the external host device based on the second clock signal. The controller requests the external host device to adjust a multiplication ratio for the frequency multiplication of the first clock signal.

Abstract: Drivers in different functional paths can use different types of identifiers for the same hardware device, such that the drivers may not be able to natively coordinate their actions related to the hardware device due to incompatible identifier types. However, a driver at a file system layer of one functional path can obtain a volume Physical Device Object (PDO) identifier at a volume layer and find a disk PDO identifier at a disk layer that is associated with the same device number. The driver can also find a parent device instance identifier from the disk PDO identifier, and use the parent device instance identifier as a plug-and-play (PnP) identifier for the hardware device during communications with a second driver in a PnP functional path.

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

Abstract: Systems, apparatuses, and methods for controlling bandwidth through shared transaction limits are described. An apparatus includes at least a plurality of agents, a plurality of transaction-limit (T-Limit) nodes, a T-Limit manager, and one or more endpoints. The T-Limit manager creates a plurality of credits for the plurality of agents to send transactions to a given endpoint. Then, the T-Limit manager partitions the credits into N+1 portions for N agents, wherein the extra N+1 portion is a shared pool for use by agents when they run out of their private credits. The T-Limit manager assigns a separate private portion of the N portions to the N agents for use by only the corresponding agent. When an agent runs out of private credits, the agent's T-Limit node sends a request to the T-Limit manager for credits from the shared pool.

Abstract: A computer sleep mode prevention device including a housing assembly, an actuation mechanism, and a connecting assembly. The housing assembly includes a housing, and actuation members. The housing is an ornamental figure. The actuation mechanism is located inside the housing. The actuation mechanism actuates the actuation members to depress a key, swipe a mouse pad or move the mouse of a computer. The connecting assembly includes a cord, the cord is connected to a computer. The connecting assembly connects the computer with the actuation mechanism. The actuation mechanism is powered through the cord. The actuation mechanism is set to actuate the actuation member in predetermined time lapses.

Abstract: An expansion base unit includes an input connector communicatively connectable with a cable to a connector in a previous base unit to allow receipt of a signal from the previous base unit, and a plurality of output connectors that each are communicatively connectable with a cable to a connector of a plurality of connectors in a subsequent expansion base unit to allow transmission of the signal received by the input connector to the subsequent expansion base unit.

Abstract: A method, computer program product, and computing system for executing a plurality of IO traces on a storage system. At least one vertical flow and at least one horizontal flow associated with the at least one vertical flow may be defined for the plurality of IO traces. A hierarchical representation of the plurality of IO traces may be generated with the at least one vertical flow and the at least one horizontal flow associated with the at least one vertical flow defined for the plurality of IO traces.

Abstract: A marine-type communication device that reads data from a data bus, dynamically creates new data channels for a plurality of operational systems and performs a volatility assessment to determine when to save the data for transmission to a cloud network and when to transmit the data to the cloud network.