Abstract: Examples relate to apparatuses, devices, methods and computer programs for a Root Complex (RC) and/or for an Endpoint (EP) of a PCIe (Peripheral Component Interconnect express) system, to a PCIe system and to a gateway device comprising a PCIe system. An apparatus configured for a RC of a PCIe system comprises a memory and one or more processors, which are configured to generate a PCIe VDM (Vendor Defined Message) message for an EP of the PCIe system.
Abstract: A controller includes a physical layer interface circuit configured to support a first port and a second port both conforming to a PCIe standard, the first port including a first number of lanes with a first order, the second port including a second number of lanes with a second order, and the first number of lanes and the second number of lanes being connected to the physical layer interface circuit via traces arranged in an order in which at least a part of the first order and at least a part of the second order are changed based on Lane Reversal conforming to the PCIe standard.
Abstract: Embodiments of the present disclosure provide a data transmission method, apparatuses, and a smart watch device. A first BLE module of a first MCU of a smart watch receives an instruction of transmitting data which includes an instruction of transmitting the data to an AP of the smart watch or a mobile terminal. The first BLE module determines whether the AP is in a wake-up state if the instruction is to transmit the data to the AP, and transmits the data to a second BLE module of the AP through a RFCOMM interface if the AP is determined to be in the wake-up state, otherwise, buffers the to-be-transmitted data. The first BLE module synchronizes state information to the second BLE module if the instruction is to transmit the data to the mobile terminal, and transmits the data to the mobile terminal through the RFCOMM interface.
Type:
Grant
Filed:
November 24, 2020
Date of Patent:
March 12, 2024
Assignee:
Mobvoi Information Technology Company Limited
Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a management processor configured to initiate a communication arrangement between a first endpoint device coupled to a communication fabric and a second endpoint device coupled to the communication fabric. The communication arrangement is configured to redirect a transfer from the first endpoint device based on an address corresponding to an address range of the second endpoint device without passing the transfer through a host processor coupled to the communication fabric that executes an application initiating the transfer.
Type:
Grant
Filed:
January 9, 2023
Date of Patent:
March 5, 2024
Assignee:
Liqid Inc.
Inventors:
James Scott Cannata, Christopher R. Long, Sumit Puri, Bryan Schramm
Abstract: The present disclosure relates to a method for booting a processing device, the method including: generating, by a monotonic counter and during a first boot phase, a first count value; transmitting, by the monotonic counter, the first count value to an access control circuit of a memory; reading, on the basis of the first count value, first data stored in the memory; and generating, by the monotonic counter and during a second boot phase, a second count value greater than the first count value. The access control circuit of the memory is configured so that the reading of the first data is not authorized on the basis of the second count value.
Type:
Grant
Filed:
March 29, 2022
Date of Patent:
February 27, 2024
Assignees:
STMicroelectronics (Alps) SAS, STMicroelectronics (Grand Ouest) SAS
Abstract: A communication apparatus includes a communication circuit, a clock supply circuit, a CPU and a memory storing a program which, when executed by the CPU, causes the communication apparatus to function as a control unit which causes the communication circuit to operate in one of a first mode in which the communication circuit performs a normal communication with the external apparatus and a second mode in which the communication circuit operates with lower power consumption than in the first mode. In the second mode, the control unit controls the clock supply circuit so as not to supply the clock signal to the communication circuit. While the communication circuit is operating in the second mode and the clock signal is not being supplied to the communication circuit, the control unit controls the clock supply circuit to start supply of the clock signal to the communication circuit in response to a predetermined signal.
Abstract: An interface of a device is used to couple to another device and includes a set of data pins to support high speed data communication on an interconnect link between the devices based on an interconnect protocol. The interface further includes at least one auxiliary pin to support a particular signal defined by the interconnect protocol. The device is further configurated to generate hint data for use by the other device and send the hint data as a sideband signal to the other device over the auxiliary pin, where the sideband signal is distinct from signals defined for the auxiliary pin by the interconnect protocol.
Type:
Grant
Filed:
May 15, 2020
Date of Patent:
February 20, 2024
Assignee:
Intel Corporation
Inventors:
Ang Li, David J. Harriman, Kuan Hua Tan
Abstract: System and method for implementing accelerated memory transfers in an integrated circuit includes identifying memory access parameters for configuring memory access instructions for accessing a target corpus of data from within a defined region of an n-dimensional memory; converting the memory access parameters to direct memory access (DMA) controller-executable instructions, wherein the converting includes: (i) defining dimensions of a data access tile based on a first parameter of the memory access parameters; (ii) generating multi-directional data accessing instructions that, when executed, automatically moves the data access tile along multiple distinct axes within the defined region of the n-dimensional memory based at least on a second parameter of the memory access parameters; transferring a corpus of data from the n-dimensional memory to a target memory based on executing the DMA controller-executable instructions.
Type:
Grant
Filed:
November 15, 2022
Date of Patent:
February 20, 2024
Assignee:
quadric.io, Inc.
Inventors:
Aman Sikka, Marian Petre, Nigel Drego, Veerbhan Kheterpal
Abstract: A management device that may communicate with at least one devices is disclosed. The management device may include a communication logic to communicate with the devices over a communication channels about data associated with the devices. The management device may also include reception logic that may receive a query from a host. The query may request information from the management device about the devices. The management device may also include a transmission logic to send the data about the devices to the host. The host may be configured to send a message to the devices.
Abstract: A host circuit includes a first clock generator, a first input output interface, a first communication interface, and a first processor. The first clock generator generates a first clock signal. The first processor outputs a trigger signal through the first input output interface, records a first clock count of the first clock generator at the same time, and outputs the first clock count through the first communication interface. A slave circuit includes a second clock generator, a second input output interface, a second communication interface, and a second processor. The second clock generator generates a second clock signal. When receiving the trigger signal, the second processor records a second clock count of the second clock generator, and calculates a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.
Abstract: Examples relate to apparatuses, devices, methods and computer programs for a Root Complex (RC) and/or for an Endpoint (EP) of a PCIe (Peripheral Component Interconnect express) system, to a PCIe system and to a gateway device comprising a PCIe system. An apparatus configured for a RC of a PCIe system comprises a memory and one or more processors, which are configured to generate a PCIe VDM (Vendor Defined Message) message for an EP of the PCIe system.
Abstract: A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. The slave devices are electrically connected together via a control line. A first slave device is configured to provide a first clock signal to each second slave device via the control line, so that a second clock signal of each second slave device is synchronized with the first clock signal. After the second clock signals are synchronized with the first clock signal, each second slave device is configured to adjust a phase of the second clock signal in a clock phase shift stage, so that each second clock signal has a phase difference with the first clock signal. The phase differences between the second clock signals of the second slave devices and the first clock signal are different.
Abstract: A interrupt control system and method based on RISC-V comprises a processor, a fast interrupt controller, a Caller-save type general-purpose register, and a hardware memory area; the hardware memory area is used for storing a value of the Caller-save type general-purpose register during an interrupt response; and the fast interrupt controller is used for storing the value of the Caller-save type general-purpose register into the hardware memory area, or loading back a content from the hardware memory area into the Caller-save type general-purpose register, and further storing a value of a control and status register set into the hardware memory area when a nested interrupt occurs; which improve an interrupt handling speed of a RISC-V architecture processor, simplify the program development difficulty, expand an application field of the RISC-V as a core single chip microcomputer, and particularly have a wide prospect in the embedded application field.
Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.
Type:
Grant
Filed:
December 9, 2022
Date of Patent:
January 16, 2024
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Kwanwoo Noh, Sungho Seo, Yongwoo Jeong, Dongwoo Nam, Myungsub Shin, Hyunkyu Jang
Abstract: A computing device that includes a first processing unit and a second processing unit that are connected to one another in a data-transmitting manner. The first processing unit, upon recognition that an activation condition is present, is configured to determine whether the activation condition requires an activation of the second processing unit, and when the activation condition requires the activation of the second processing unit, to activate the second processing unit and to output an activation signal, including the activation condition, on an activation line. Also, a network that includes at least two such computing devices, and a method for activating a second processing unit of a computing device that includes a first processing unit and the second processing unit, which are connected to one another in a data-transmitting manner, are also described.
Type:
Grant
Filed:
February 10, 2022
Date of Patent:
January 9, 2024
Assignee:
ROBERT BOSCH GMBH
Inventors:
Andre Owerfeldt, Domenic Garcea, Lambros Dalakuras, Liem Dang
Abstract: A data transfer system includes a bus system; a master unit; at least one slave unit, which is allocated to the master unit and is designed to send interrupt requests directed to the master unit; and a monitor unit, which is connected between the master unit and the bus system. The monitor unit receives messages sent by the master unit and the interrupt requests sent by each slave unit allocated to the master unit. Polling messages directed by the master unit to an allocated slave unit are not forwarded by the monitor unit to the bus system until the slave unit sends an interrupt request via an interrupt request line.
Type:
Grant
Filed:
August 4, 2021
Date of Patent:
January 9, 2024
Assignee:
Siemens Aktiengesellschaft
Inventors:
Aharón Jesús Vargas Barroso, Christian Wagner
Abstract: A management device that may communicate with at least one devices is disclosed. The management device may include a communication logic to communicate with the devices over a communication channels about data associated with the devices. The management device may also include reception logic that may receive a query from a host. The query may request information from the management device about the devices. The management device may also include a transmission logic to send the data about the devices to the host. The host may be configured to send a message to the devices.
Abstract: A management device that may communicate with at least one devices is disclosed. The management device may include a communication logic to communicate with the devices over a communication channels about data associated with the devices. The management device may also include reception logic that may receive a query from a host. The query may request information from the management device about the devices. The management device may also include a transmission logic to send the data about the devices to the host. The host may be configured to send a message to the devices.
Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.
Type:
Grant
Filed:
December 13, 2022
Date of Patent:
December 26, 2023
Assignees:
STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS (GRENOBLE 2) SAS
Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.
Type:
Grant
Filed:
January 24, 2022
Date of Patent:
December 26, 2023
Assignee:
MELLANOX TECHNOLOGIES, LTD.
Inventors:
Dotan David Levi, Wojciech Wasko, Eitan Zahavi, Natan Manevich, Bar Shapira