Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a vertical three-dimensional semiconductor device and a method for manufacturing such a device. In one aspect, the vertical three-dimensional semiconductor device has a source layer formed over a substrate. A horizontal stack of alternating electrically isolating layers and electrically conductive gate layers are formed over the source layer, wherein one of the electrically isolating layers contacts the source layer. A vertical channel structure extends vertically through the horizontal stack of alternating layers. A drain is formed over the horizontal stack of alternating layers and over the vertical channel structure. The source layer is configured to inject charge carriers into the vertical channel structure, and the metal drain is configured to extract charge carriers from the vertical channel structure.

Abstract: An image sensor includes a substrate, a plurality of light sensitive pixels, a first plurality of color filters, a plurality of reflective sidewalls, and a second plurality of color filters. The light sensitive pixels are formed on said substrate. The first plurality of color filters is disposed over a first group of the light sensitive pixels. The reflective sidewalls are formed on each side of each of the first plurality of color filters. The second plurality of color filters are disposed over a second group of light sensitive pixels and each color filter of the second plurality of color filters is separated from each adjacent filter of said first plurality of color filters by one of the reflective sidewalls. In a particular embodiment an etch-resistant layer is disposed over the first plurality of color filters and the second group of light sensitive pixels.

Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In general, the ohmic contact structure has a root-mean-squared (RMS) surface roughness of less than 10 nanometers, and more preferably less than or equal to 7.5 nanometers, and more preferably less than or equal to 5 nanometers, and more preferably less than or equal to 2 nanometers, and even more preferably less than or equal to 1.5 nanometers.

Abstract: In a semiconductor device, a gate insulating film is provided with a multi-layer structure including a first insulating film and a second insulating film. The first insulating film is formed of an insulating film containing an element having an oxygen binding force larger than that of an element contained in the second insulating film, and the total charge amount is increased. Specifically, by performing oxygen anneal, it is possible to perform the step of supplying oxygen into an aluminum oxide film and increase the total charge amount. This allows a negative fixed charge density in the gate insulating film in the vicinity of an interface with a GaN layer to be set to a value of not less than 2.5×1011 cm?2 and allows a normally-off element to be reliably provided.

Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

Abstract: Aspects of the present disclosure include a semiconductor test device and method. The test device includes a first Kelvin testable structure and a second Kelvin testable structure. The first Kelvin testable structure includes an upper metal plate, a plurality of dummy vias and one measurement via under and electrically connected to the upper plate and a lower metal island electrically connected to the one measurement via. The second Kelvin testable structure includes an upper reference metal plate, a reference via under and electrically connected to the upper reference metal plate, and a lower metal reference island electrically connected to the reference via.

Abstract: A MEMS device includes a substrate, a supporter, a first back plate, a second back plate and a diaphragm. The substrate has a cavity. The supporter is over the substrate. The first back plate is over the cavity and fixed on the supporter. The second back plate is over the cavity and fixed on the supporter. The diaphragm is between the first back plate and the second back plate. The diaphragm includes a first sub-diaphragm and a second sub-diaphragm over the cavity and fixed on the supporter.

Abstract: The present disclosure provides a semiconductor structure includes a semiconductor layer having a surface, and an interlayer dielectric (ILD) defining a metal gate over the surface of the semiconductor layer. The metal gate includes a high-k dielectric layer, a capping layer, and a work function metal layer. A thickness of the capping layer sidewall distal to a corner of the capping layer, is substantially thinner than a thickness which is around center of the capping layer bottom. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate recess, forming a high-k dielectric layer, forming a first capping layer, forming a second capping layer on the first capping layer, removing or thinning down the first capping layer sidewall, and removing the second capping layer.

Abstract: A method for producing a semiconductor device includes forming a semiconductor-pillar on a substrate and forming a laminated-structure of at least two composite layers, each including a metal layer and a semiconductor layer in contact with the metal layer, the semiconductor layer containing donor or acceptor atoms, and two interlayer insulating layers sandwiching the composite layers, such that a side surface of at least one of the two interlayer insulating layers is separated from a side surface of the semiconductor pillar. The laminated-structure surrounds the semiconductor pillar. A first heat treatment causes a reaction between the metal layer and the semiconductor layer to form an alloy layer, and brings the alloy layer into contact with the side surface of the semiconductor pillar. A second heat treatment to expands the alloy layer into the semiconductor pillar and diffuses dopant atoms into the semiconductor pillar to form an impurity region therein.

Abstract: A physical quantity sensor includes a base substrate; a movable unit which is provided so as to be displaced with respect to the base substrate by facing the base substrate; a first fixed electrode and a second fixed electrode which are disposed on the base substrate by facing the movable unit; and a plurality of protrusion portions which are disposed at a position overlapped with the movable unit in a planar view, on the movable unit side of the base substrate, in which the protrusion portion includes a conductive layer with the same potential as that of the first fixed electrode and the second fixed electrode, and an insulating layer which is provided on a side opposite to the base substrate with respect to the conductive layer.

Abstract: A semiconductor crystal substrate includes a substrate, a first semiconductor layer including a nitride semiconductor and formed over the substrate, a second semiconductor layer including a nitride semiconductor and formed over the first semiconductor layer, a first cap layer formed on the second semiconductor layer, and a second cap layer formed on the first cap layer. Each of the first semiconductor layer and the second semiconductor layer has a single-crystal structure, the first cap layer has one of a single-crystal structure and a polycrystalline structure, and the second cap layer has an amorphous structure.

Abstract: A method for fabricating high-resolution features in a deep recess includes etching a cavity in a substrate, fabricating at least one focusing pattern on a bottom of the cavity, wherein fabricating the focusing pattern comprises coating a first photoresist on the bottom of the cavity, patterning the first photoresist to define a focusing etch area using contact lithography, and etching the focusing etch area, coating a second photoresist on the bottom of the cavity, using the focusing pattern to focus a high resolution lithography tool at the bottom of the cavity to pattern the second photoresist to define a microfabrication feature area; and forming a microfabrication feature in the microfabrication feature area.

Abstract: There is provided a light emitting device including: a semiconductor substrate; a plurality of pixel circuits that is disposed in a display region of the semiconductor substrate; a first wiring that is formed of a conductive material so as to be supplied with a predetermined electric potential; and a plurality of first contact portions that is formed of a conductive material so as to connect the semiconductor substrate and the first wiring. The plurality of first contact portions and the first wiring are provided in the display region.

Abstract: A display substrate and a fabrication method thereof and a display device. The display substrate includes: a plurality of pixels disposed on a lower substrate; and a pixel defining layer disposed between adjacent pixels of the plurality of pixels, the pixel defining layer contacting with an upper substrate of the plurality of pixels, the pixel defining layer configured for defining each pixel and supporting a gap between the upper substrate and the lower substrate.

Abstract: A ring-type FET may include a silicon base, a source formed on a portion of the silicon base through doping, a channel formed to encompass the source on a plane, a drain formed outside the channel, a dielectric layer formed on the source, the channel and the drain, and a gate provided on the dielectric layer, wherein a center of the source is spaced apart from a center of the channel, and the gate is formed of a metal material, disposed above the channel and configured to cover an upper face of the channel and overlap a portion of the source and a portion of the drain.

Abstract: Disclosed are an oxide thin film transistor and a method of fabricating the same. The oxide thin film transistor according to an embodiment of the present disclosure includes a gate electrode formed on a substrate, a gate insulating layer formed on the gate electrode, an oxide semiconductor layer as a semiconductor active layer, and source and drain electrodes formed on the oxide semiconductor layer. The oxide semiconductor layer is activated by heat of less than 300° C. and a change in the magnetic flux of an applied magnetic field. More specifically, the activation proceeds by activation energy provided by Joule heat generated from eddy current occurring in the oxide semiconductor layer by a change in the magnetic flux, and the heat of less than 300° C.

Abstract: The thin film transistor includes a gate electrode formed on a surface of a substrate; a first amorphous silicon layer formed on an upper side of the gate electrode; a plurality of polysilicon layers separated by the first amorphous silicon layer and formed on the upper side of the gate electrode with a required spaced dimension; a second amorphous silicon layer and an n+ silicon layer which are formed on the upper side of the plurality of polysilicon layers and the first amorphous silicon layer; and a source electrode and a drain electrode formed on the n+ silicon layer.

Abstract: The disclosed technology relates to electronics, and more particularly, to protection devices that protect circuits from transient electrical events such as electrical overstress/electrostatic discharge. A protection device includes a semiconductor substrate having formed therein at least two wells and a deep well underlying and contacting the at least two wells. The device additionally includes a first PN diode formed in one of the at least two wells and having a first heavily doped region of a first conductivity type and a first heavily doped region of a second conductivity type, and includes a second PN diode formed in one of the at least two wells and having a second heavily doped region of the first conductivity type and a second heavily doped region of the second conductivity type. The device additionally includes a first PN diode and the second PN diode are electrically shorted by an electrical shorting structure to form a first plurality of serially connected diodes having a threshold voltage.