Abstract: A package carrier is provided. The package carrier includes a wiring layer and an insulating pattern. The wiring layer includes at least one connecting pad and at least one mounting pad. The mounting pad is used for mounting an electronic component, and the connecting pad is used for electrically connecting the electronic component. The insulating pattern is stacked on and connected to the wiring layer. A boundary surface is formed between the wiring layer and the insulating pattern. Both of the wiring layer and the insulating pattern do not extend over the boundary surface. In addition, an electronic package including the package carrier is also provided.

Abstract: A light-emitting device is provided. The light-emitting device comprises: a light-emitting stack having an active layer emitting first light having a peak wavelength ? nm; and an adjusting element stacked electrically connected to the active layer in series for tuning a forward voltage of the light-emitting device; wherein the forward voltage of the light-emitting device is between (1240/0.8?) volt and (1240/0.5?) volt.

Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.

Abstract: Method of producing bonded wafer including thin film on base wafer, including: implanting at least one gas ion selected from hydrogen ion and rare gas ion into bond wafer from surface of bond wafer to form layer of implanted ion; bonding surface from which ion is implanted into bond wafer and surface of base wafer directly or through insulator film; and then performing heat treatment to separate part of bond wafer along layer of implanted ion, wherein before bond wafer and base wafer are bonded, thickness of bond wafer and base wafer is measured, and combination of bond wafer and base wafer is selected such that difference in thickness between the wafers is less than 5 ?m, and selected bond and base wafers are bonded. This method can inhibit variation in thickness in marble pattern that occurs in thin film and produce bonded wafer including thin film with uniform thickness.

Abstract: Methods of forming III-V LED structures on silicon fin templates are described. Those methods and structures may include forming an n-doped III-V layer on a silicon (111) plane of a silicon fin, forming a quantum well layer on the n-doped III-V layer, forming a p-doped III-V layer on the quantum well layer, and then forming an ohmic contact layer on the p-doped III-V layer.

Abstract: A display device according to an embodiment of the present disclosure may include a lower substrate disposed with a line electrode at an upper portion thereof, a plurality of semiconductor light emitting devices electrically connected to the line electrode to generate light, a wavelength converter disposed on the semiconductor light emitting device to convert a wavelength of light generated from the semiconductor light emitting device, and a conductive adhesive layer comprising conductors configured to electrically connect the lower substrate to the semiconductor light emitting device and a body configured to surround the conductors, wherein the semiconductor light emitting device has a composition formula of InxAlyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1).

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. An alternating sequence of support pedestal structures and conductive rail structures extending along a same horizontal direction are provided between the substrate and the alternating stack. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support pedestal structure. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure, and is electrically isolated from an adjacent support pedestal structure by a portion of a memory film. The conductive rail structures can function as source regions of memory device.

Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film, and an array of dielectric pillars located between the alternating stack and the substrate.

Abstract: Provided is a vertical MOSFET in which a conduction deterioration phenomenon is prevented during a current return operation and an on-voltage is low during the current return operation. A semiconductor device includes a hole barrier region that is provided between a second-conductivity-type body region and a first-conductivity-type epitaxial layer below a second-conductivity-type body contact region and functions as a potential barrier to a hole which flows from a source electrode to the first-conductivity-type epitaxial layer through the second-conductivity-type body contact region and the second-conductivity-type body region.

Abstract: In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.

Abstract: A dielectric material layer is deposited on gate structures of first and second semiconductor material portions. The dielectric material layer is anisotropically etched to form a first gate spacer on a first semiconductor material portion, while being protected above the second semiconductor material portion. After formation of first raised active regions on the first semiconductor material portion, a dielectric stack of a dielectric oxide liner and a dielectric nitride liner is formed. The dielectric stack is removed over the second semiconductor material portion and a second gate spacer is formed on the second semiconductor material portion, while the dielectric stack protects the first raised active regions. A second gate spacer is formed by anisotropically etching the dielectric material layer over the second semiconductor material portion. The first and second gate spacers have the same composition and thickness. Second raised active regions can be formed on the second semiconductor material portion.

Abstract: A semiconductor structure includes a substrate, at least one active semiconductor fin, at least one insulating structure, a gate electrode, and a gate dielectric. The active semiconductor fin is disposed on the substrate. The insulating structure is disposed on the substrate and adjacent to the active semiconductor fin. A top surface of the insulating structure is non-concave and is lower than a top surface of the active semiconductor fin. The gate electrode is disposed over the active semiconductor fin. The gate dielectric is disposed between the gate electrode and the active semiconductor fin.

Abstract: A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.

Abstract: A method of forming patterns of a semiconductor device, including partially etching an upper portion of a substrate to form first preliminary active patterns and a first trench, each of the first preliminary active patterns having a first width, and the first trench having a second width of about 2 to 3 times the first width; forming an insulating spacer on each sidewall of the first trench to form a second trench having the first width; forming a second preliminary active pattern in the second trench, the second preliminary active pattern having the first width; partially etching the first and second preliminary active patterns to form a plurality of first active patterns and a plurality of second active patterns and an opening between the plurality of first and second active patterns; and forming an insulation pattern to fill the opening.

Abstract: A light-emitting element includes: a semiconductor light-emitting stack including a first semiconductor layer with a first conductivity, an active layer, and a second semiconductor layer with a second conductivity; a first conductive layer disposed on the semiconductor light-emitting stack and electrically connecting the second semiconductor layer; a first insulating layer on the first conductive layer; a second conductive layer disposed on the first insulating layer and electrically connecting the first semiconductor layer; a second insulating layer on the second conductive layer; a first pad and a second pad on the second conductive layer; and a cushion part disposed between the first pad and the second pad.

Abstract: An insulated gate semiconductor device provided herein includes a front electrode and a rear electrode and is configured to switch a conducting path between the front electrode and the rear electrode. The insulated gate semiconductor device includes a first circumferential trench provided in the front surface; a second circumferential trend provided in the front surface and deeper than the first circumferential trench; a fifth region of a second conductivity type exposed on a bottom surface of the first circumferential trench; a sixth region of the second conductivity type exposed on a bottom surface of the second circumferential trench; and a seventh region of a first conductivity type connected to the third region and separating the fifth region from the sixth region. A front side end portion of the sixth region being located on a rear side with respect to a rear side end portion of the fifth region.

Abstract: The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L5) is laid which functions as a source of a power transistor (Q3) and a cathode of a diode (D4), and further functioning as a drain of a power transistor (Q4) and an anode of a diode (D3). In other words, a power transistor and a diode coupled to this power transistor in series are formed in the same semiconductor chip; and further an interconnect functioning as a drain of the power transistor and an interconnect functioning as an anode of the diode are made common to each other. This structure makes it possible to decrease a parasite inductance between the power transistor and the diode coupled to each other in series.

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.

Abstract: A pixel structure includes a metal oxide semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, a passivation layer, a second conductive layer and a pixel electrode. The metal oxide semiconductor layer includes a second semiconductor pattern. The first insulating layer includes a first capacitance dielectric pattern disposed on the second semiconductor pattern. The second insulating layer includes a second capacitance dielectric pattern disposed on the first capacitance dielectric pattern. The first conductive layer includes a electrode pattern disposed on the second capacitance dielectric pattern. The passivation layer covers the first conductive layer. The second conductive layer includes a second electrode disposed on the passivation layer. The second electrode is electrically connected to the second semiconductor pattern. The second electrode is disposed to overlap the electrode pattern.