Patents Examined by Ha Tran Nguyen
  • Patent number: 9406717
    Abstract: A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: August 2, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8866223
    Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 21, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Alfio Guarnera, Mario Giuseppe Saggio, Ferruccio Frisina
  • Patent number: 8802468
    Abstract: A semiconductor light emitting device includes a lower cladding layer, an active layer, and an AlGaAs upper cladding layer mounted on a GaAs substrate. The semiconductor light emitting device has a ridge structure including the AlGaAs upper cladding layer. The semiconductor light emitting device further includes an InGaAs etching stop layer provided in contact with the lower side of the AlGaAs upper cladding layer. The InGaAs etching stop layer has a band gap greater than that of the active layer.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: August 12, 2014
    Assignees: Fujitsu Limited, The University of Tokyo
    Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Hisao Sudo, Yasuhiko Arakawa
  • Patent number: 8741780
    Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph Ervin, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 8080826
    Abstract: The present invention discloses and claims the Silicon Carbide based Silicon structure comprising: (1) a Silicon Carbide substrate, (2) a Silicon semiconductor material having a top surface, and either bonded to the Silicon Carbide substrate via the bonding layer, or epitaxially grown on the Silicon Carbide substrate; and (3) at least one separation plug formed in the Silicon semiconductor material. The single bonding layer, or either layer of the double bonding layer, is selected from the group consisting of: {a Silicon dioxide layer; a Silicon layer; a carbon layer; a Silicon germanium (SiGe) layer; a tungsten silicide layer; a titanium suicide layer; and a cobalt silicide layer}. The separation plug extends from the top surface of the Silicon semiconductor material into the Silicon Carbide substrate at a separation plug depth level, and is configured to block the coupling between at least two adjacent active/passive structures formed in the Silicon semiconductor material.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: December 20, 2011
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph H. Johnson, Pablo D'Anna
  • Patent number: 8026539
    Abstract: Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: September 27, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Michael Hargrove, Frank Bin Yang, Rohit Pal
  • Patent number: 7932734
    Abstract: A storage device transporter is provided for transporting a storage device and for mounting a storage device within a test slot. The storage device transporter includes a frame that is configured to receive and support a storage device. The storage device transporter also includes a conductive heating assembly that is associated with the frame. The conductive heating assembly is arranged to heat a storage device supported by the frame by way of thermal conduction.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: April 26, 2011
    Assignee: Teradyne, Inc.
    Inventors: Brian S. Merrow, Larry W. Akers
  • Patent number: 7919975
    Abstract: A differential signaling system, wherein a first wiring and a second wiring are coupled between a sending end and a receiving end as a differential signal line. A termination resistor is coupled between the first wiring and the second wiring in the receiving end side. A test circuit is coupled to the termination resistor in parallel, and amplifies and detects a variation of a differential impedance due to the differential signal line. The test circuit includes: a differential test amplifier for amplifying a variation in the differential impedance of the first wiring or the second wiring; a switching unit installed at an input terminal of the differential test amplifier for controlling an operation of the differential test amplifier; and a peak detector for converting an output signal of the differential test amplifier into a direct current component; and a phase detector for detecting a skew, a time delay, and/or a phase difference of a signal inputted to the differential signal line.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: April 5, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventor: Jee-youl Ryu
  • Patent number: 7749893
    Abstract: The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: July 6, 2010
    Assignee: Lam Research Corporation
    Inventors: Fritz Redeker, John Boyd, Yezdi Dordi, Hyungsuk Alexander Yoon, Shijian Li
  • Patent number: 7674642
    Abstract: Green light emitting diodes (LED) of gallium arsenide (GaAs) are series-connected. The series connection has a small transmission attenuation and a wide bandwidth. The GaAs LED has a big forward bias and so neither extra driving current nor complex resonant-cavity epitaxy layer is needed. Hence, the present invention has a high velocity, a high efficiency and a high power while an uneven current distribution is avoided.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: March 9, 2010
    Assignee: National Central University
    Inventors: Jin-Wei Shi, Jinn-Kong Sheu, Mao-Jen Wu, Chun-Kai Wang, Cheng-Hiong Chen, Jen-Inn Chyi
  • Patent number: 7670884
    Abstract: The manufacturing method of a substrate having a conductive layer has the steps of: forming an inorganic insulating layer over a substrate; forming an organic resin layer with a desired shape over the inorganic insulating layer; forming a low wettability layer with respect to a composition containing conductive particles on a first exposed portion of the inorganic insulating layer; removing the organic resin layer; and coating a second exposed portion of the inorganic insulating layer with a composition containing conductive particles and baking, thereby forming a conductive layer.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: March 2, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Gen Fujii, Masafumi Morisue, Hironobu Shoji, Junya Maruyama, Kouji Dairiki, Tomoyuki Aoki
  • Patent number: 7671619
    Abstract: A measuring system comprises a pulse generator, an under test device, a variable resistor and a detecting control system. The pulse generator provides pulse signals with different voltage peaks to the under test device and the variable resistor. The variable resistor adjusts its resistance value according to a control signal. The detecting control system detects the voltage ringing ranges of the first terminal of the under test device at different resistance values. The detecting control system generates the control signal to adjust the resistance value of the variable resistor according to the voltage ringing ranges.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: March 2, 2010
    Assignee: TPO Displays Corp.
    Inventors: Wei-Cheng Lin, Cheng-Ho Yu
  • Patent number: 7659741
    Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: February 9, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7656171
    Abstract: A method and apparatus for detecting defects includes irradiating and scanning an electron beam focused on an area of a sample, detecting charged particles generated from the sample by the irradiating and scanning of the electron beam with a first detector which detects charged particles having relatively low energy to obtain a first image of the area and with a second detector which detects charged particles having relatively high energy to obtain a second image of the area, comparing the first inspection image of the area with a first reference image to generate a first difference image, and comparing obtained second image of the area with a second reference image to generate a second difference image, and detecting an open defect or a short defect from at least one of the generated first difference image and the second difference image.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: February 2, 2010
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Toshifumi Honda, Takehiro Hirai
  • Patent number: 7642791
    Abstract: In one embodiment, an interposer is made of a flexible, non-electrically conductive material with electrically conductive paths formed therein to substantially correspond with a pattern of electrical contacts of an electronic component and with a pattern of electrical contacts of an interface to be coupled to the electronic component.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: January 5, 2010
    Assignee: Intel Corporation
    Inventor: Jeff Burgess
  • Patent number: 7632751
    Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: December 15, 2009
    Assignee: Panasonic Corporation
    Inventor: Takeshi Harada
  • Patent number: 7626411
    Abstract: The present invention provides a semiconductor device, including: a first semiconductor chip, and a second semiconductor chip connected to the first semiconductor chip through a plurality of bumps having not only a number of main bumps necessary for operation between the chips but also a predetermined number of measurement and control input bumps. Each of the first and second chips includes a plurality of measurement path switches individually connected to the main bumps, a plurality of current path switches connected to connecting points between the main bumps and the measurement path switches, and a control circuit for the measurement path switches, the first semiconductor chip further including a plurality of measurement and control terminals for inputting a control signal of the control circuit and supplying fixed current to be supplied to the current path switches and then measuring the voltage at the connecting points.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: December 1, 2009
    Assignee: Sony Corporation
    Inventors: Kazutoshi Shimizume, Takaaki Yamada
  • Patent number: 7586323
    Abstract: A liquid crystal display (LCD) inspection apparatus and method are provided. The inspection apparatus and method are capable of automatically and accurately detecting defects of an LCD panel, and providing information of the automatically-detected defects of the LCD panel to the operator, thereby enabling the operator to easily recognize the defects.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: September 8, 2009
    Assignee: LG. Display Co., Ltd.
    Inventors: Dong Woo Kang, Soung Yeoul Eom, Bong Chul Kim, Ki Soub Yang
  • Patent number: 7545162
    Abstract: An apparatus of inspecting a liquid crystal display device includes a magnetic sensor scanning a signal line pattern on a substrate to detect a defective position of the signal line pattern, a camera imaging the signal line pattern detected by the magnetic sensor, an inspecting jig contacting a probe pin with the signal line pattern to determine the existence of defective in the signal line pattern, a transferring tool system transferring at least one of the substrate, the magnetic sensor and the camera in a two-axis direction, and a controller controlling the magnetic sensor, the camera, the inspecting jig and the transferring tool system.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: June 9, 2009
    Assignee: LG Display Co., Ltd.
    Inventor: Han Rok Chung
  • Patent number: 7541216
    Abstract: A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: June 2, 2009
    Assignee: Nantero, Inc.
    Inventors: Colin D. Yates, Christopher L. Neville