Abstract: A method is presented of designing semiconductor probe cards to have the optimum number and placement of die probe sites for function testing integrated circuit (IC) die at semiconductor wafer test, while minimizing the number of times the probe card must be moved (number of “touchdowns”) to test all the IC die on a semiconductor wafer, as well as minimizing the number of individual IC die on the wafer that are probed more than once during the wafer test. Each specific arrangement of probe sites is tested against other patterns for efficiency in testing in what is known as a genetic algorithm. The most efficient patterns are moved into the next generation with modified features obtained by crossovers between two efficient individuals, and with random mutations, until a selected efficiency is obtained, or until a maximum number of generations have occurred.

Abstract: A test fixture, for testing an electronic device, includes: a test platform including electrically conductive contacts protruding from a device receiving surface in the test platform; a positioning guide disposed on the device receiving surface; a device retention cover; where the test platform includes a platform magnetic member and the retention cover includes a cover magnetic member, the platform magnetic member and the cover magnetic member being mutually magnetically attractive. A method of producing an electronic device including: preparing the test fixture, for testing the electronic device; placing the electronic device using the at least one device positioning guide disposed on the device receiving surface; and placing the device retention cover upon the electronic device to apply a force to the electronic device.

Abstract: A method for error detection in a drive mechanism, having a multiphase electric motor and a converter connected upstream thereof, wherein the converter controls voltages of individual phases of the electric motor, and individual phase currents in the individual phases of the electric motor each extend periodically. The method includes measuring a phase current of the electric motor at a predetermined point of a respective period, simultaneously varying a voltage that is associated with the measured phase current and evaluating a measured value of the measured phase current as a function of the voltage that is associated with the measured phase current.

Abstract: A method and a relative test structure for measuring the coupling capacitance between two interconnect lines exploits the so-called cross-talk effect and keeps an interconnect line at a constant reference voltage. This approach addresses the problem of short-circuit currents that affect known test structures, and allows a direct measurement of the coupling capacitance between the two interconnect lines. Capacitance measurements may also be used for determining points of interruption of interconnect lines. When a line is interrupted, the measured coupling capacitance is the capacitance of a single conducting branch. The position of points of interruption of an interconnect line is determined by measuring the coupling capacitance of all segments of the line with a second conducting line.

Abstract: Improved methods and apparatuses for automatically and accurately maintaining the alignment of a wafer prober to the bonding pads of a semiconductor device in the presence of motion disturbances are provided. In one embodiment of one aspect of the invention, a feedback control system incorporating information from a number of acceleration and/or velocity sensors is used to maintain the desired contact position in the presence of motion disturbances. Other aspects and other embodiments are also described.

Abstract: The present invention relates to a device 1 for measuring an electric current and is particularly well adapted to electricity counters. This device 1 comprises a primary conductor 2 having a general U-shape, said primary conductor comprising a core 16 substantially circular in shape centred on an axis C, said central axis, and two branches, said first 19 and second 20 branches and a secondary winding 6 sensitive to a magnetic field, said secondary winding being disposed between said first 19 and second 20 branch of said primary conductor 2. Said primary conductor 2 is a flat profile folded in a U, said first branch 19 exhibiting torsion 13 of an angle of 90° according to a first direction of torsion and said second branch 20 exhibiting torsion 12 according to an angle of 90° along a second direction of torsion.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: By decreasing the amount of card substrate required in a memory card to support the actual memory unit, the test interface of the card, which is usually removed before final assembly of the card, can be brought within the allowable length of the finished card and can, therefore, remain on the card permanently. Consequently, in the event of a field failure, the test interface remains available for testing the card and diagnosing the location and cause of the failure.

Abstract: Sensing current flowing through a semiconductor device includes providing an input pin to receive an input, providing an output pin coupled to a predefined voltage source, providing a control pin to receive a control signal for controlling a flow of current between the output pin and the input pin, and electrically coupling a Kelvin sense pin to an output pad located on a semiconductor die of the device. An electrical path from the output pad to the output pin has a predefined resistance. The current is Kelvin current sensed using the predefined resistance. A flow of an output current provided to a load coupled to the device is interrupted when a value of the current is greater than a predefined value.

Abstract: A test system configuration is provided to enable testing of integrated circuit (IC) packages. The test system includes a test controller, an interface apparatus including a PC board with lines connecting the test controller to contact areas for contacting the IC packages and a handler for supporting the IC chips and interface apparatus to maintain electrical connections during testing. The handler includes docking plates for attaching to the PC board to provide a guide for the IC packages that are inserted in openings of the docking plates to align contacts of the IC packages and PC board. The docking plates are configured to provide quad (four) and octal (eight) test sites, with either the quad or octal docking plate mating to the same PC board and being supported in the same handler system. An alignment frame for mounting either the quad or octal docking plate is further provided as part of the handler.

Abstract: A digitizing ohmmeter system for providing a digital resistance ratio measurement includes a high impedance current source providing a DC excitation current to an impedance-varying input sensor and a reference resistor and an ADC circuit including a charge-balancing modulator and a digital post processing circuit. The same DC excitation current passes through both the input sensor and the reference resistor. The system utilizes a switched capacitor input stage to sample the voltage across the input sensor and the voltage across the reference resistor to generate an input voltage step and a reference voltage step which are coupled to the modulator of the ADC circuit. The digitizing ohmmeter system thereby realizes fully ratiometric operation such that neither a precise current source nor a precise voltage source is required for accurate resistance ratio measurements and only a stable known reference resistor is necessary for accurate absolute resistance measurements.

Abstract: An integrated circuit device disclosed herein includes a test device and a setup and hold measuring circuit. The setup and hold measuring circuit generates a reference signal and a data signal in response to an external clock signal in a test mode of operation. The test device receives the data signal in response to a reference signal, and outputs the inputted data signal as a setup and hold determining circuit. One of the reference signal and the data signal is a multiphase signal synchronized with the external clock signal. The setup and hold measuring circuit detects whether the output of the test device indicates a valid value of the data signal, and generates the detected result to the external as a setup/hold timing margin through at least one pad.

Abstract: A test chip module for testing the integrity of the flip chip solder ball interconnections between chip and substrate. The interconnections are thermally stressed through an array of individual heaters formed in a layer of chip metallurgy to provide a uniform and ubiquitous source of heat. Current is passed through the interconnection to be tested by a current supply circuit using one signal I/O interconnection and the voltage drop across the interconnection to be tested from the current passed therethrough is measured by a voltage measuring circuit connected through another signal I/O interconnection. Stress initiating cracking and degradation at the interconnection creates a measurable change in voltage drop across the interconnection.

Abstract: A method and apparatus for achieving electrical conductivity that can, for instance, obviate the need for the use of two hands to make a measurement of electrical properties across two contacts that do not lend themselves to the acceptance of clip-on leads, or across contacts that are located where access is difficult. Probes constructed partially with ferromagnetic materials and small permanent magnets provide the connectivity and conductivity of the present invention.

Abstract: Some embodiments of the invention include apparatus and systems having integrated circuits. Terminals or pins of the integrated circuits are configured to be driven to a state, to be floated for a time interval, and to be measured to determine the state of the terminals after the time interval. The measurement involves sampling the RC time constant of leakage current of the terminals. Other embodiments are described and claimed.

Abstract: A method and apparatus are provided for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup. A separate power distribution is provided for coupling a positive voltage supply rail to the N well and a ground voltage supply rail to the P well of the CMOS circuit. At least one sensor monitors current flow in a bias voltage applied to at least one of an N well and a P well of the CMOS circuitry. A latchup event is detected responsive to a predefined increase in the monitored current flow. A switch temporarily interrupts the connection of at least one of the N well and the P well to the respective voltage supply rail when the latchup event is detected.

Abstract: There is provided a voltage generating apparatus that outputs a power source voltage from a voltage outputting terminal.

Abstract: Regulating a direct current-to-direct current (DC-DC) converter, a semiconductor switch having an improved current sensing technique is used to switch a DC voltage input at a predefined frequency. The switch includes a control pin to receive a control signal for controlling a current flowing between an input pin and an output pin. The switch also includes a Kelvin sense pin electrically coupled to an output pad located on a semiconductor die of the device for sensing the current. An electrical path from the output pad to the output pin in the form of a conductive lead wire has a predefined resistance. The current is Kelvin current sensed using the predefined resistance to tightly control deviation in the current beyond a predefined range.

Abstract: Method and apparatus using a retention arrangement with a potting enclosure for holding a plurality of probes by their retention portions, the probes being of the type having contacting tips for establishing electrical contact with pads or bumps of a device under test (DUT) to perform an electrical test. The retention arrangement has a top plate with top openings for the probes, a bottom plate with bottom openings for the probes, the plates being preferably made of ceramic with laser-machined openings, and a potting enclosure between the plates for admitting a potting agent that upon curing pots the retaining portions of the probes. In some embodiments a spacer is positioned between the top and bottom plates for defining the potting enclosure. Alternatively, the retention arrangement has intermediate plates located in the potting enclosure and having probe guiding openings to guide the probes.

Abstract: A system for testing semiconductor components includes an interconnect, an alignment system for aligning a substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. The system can be utilized with a method that includes the steps of bonding the interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component.