Patents Examined by Ha Tran T Nguyen
  • Patent number: 9564426
    Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: February 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tohru Kawai, Yasutaka Nakashiba, Yutaka Akiyama
  • Patent number: 9559118
    Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: January 31, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Gurtej S. Sandhu
  • Patent number: 9541273
    Abstract: A heat dissipation structure of an SMD LED includes a substrate, an SMD LED and at least one engaging member. A plurality of conductive copper foils is covered on an upper end face of the substrate. Two electrodes are provided on a lower surface of the SMD LED and are respectively connected to two copper foils on the upper end face. An engaging hole extends through one of the copper foils adjacent the SMD LED and through the substrate. The engaging member is made of high thermal conductive metal and is engaged in the engaging hole to combine the copper foil and the substrate. Accordingly, heat generated by the SMD LED can be directly transferred to an exposed lower end face of the substrate through the engaging member for more heat dissipation and less luminance decrease of the SMD LED.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: January 10, 2017
    Inventor: Wen-Sung Hu
  • Patent number: 9536862
    Abstract: Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 3, 2017
    Assignee: Invensas Corporation
    Inventors: Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram
  • Patent number: 9530726
    Abstract: A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: December 27, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-jin Moon, Byung-Iyul Park, Dong-chan Lim, Deok-young Jung, Gil-heyun Choi, Dae-lok Bae, Pil-kyu Kang
  • Patent number: 9524989
    Abstract: Embodiments of the present invention disclose an array substrate and a method of manufacturing the same, and a liquid crystal display screen.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: December 20, 2016
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Tong Yang, Guolei Wang
  • Patent number: 9520462
    Abstract: Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate including a dopant material of a first conductivity type. A plurality of trenches are formed within the substrate. The semiconductor devices also include a diffusion region having dopant material of a second conductivity type formed proximate to the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor includes at least a first electrode, a second electrode, and a dielectric material formed between the first and second electrodes.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: December 13, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Khanh Tran, Joseph P. Ellul, Anuranjan Srivastava, Kiyoko Ikeuchi, Scott W. Barry
  • Patent number: 9520501
    Abstract: The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: December 13, 2016
    Assignee: FinScale Inc.
    Inventors: Viktor I. Koldiaev, Rimma A. Pirogova
  • Patent number: 9515095
    Abstract: The invention belongs to the field of display technology, and particularly provides an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and a thin film transistor and at least one driving electrode provided on the base substrate, and the thin film transistor includes a gate, and a source and a drain provided in the same layer, wherein the gate, the source or the drain is formed with the same material as the at least one driving electrode, and thickness thereof is larger than that of the at least one driving electrode. Regarding the array substrate, the manufacturing procedure of the array substrate is effectively simplified, cost for mask plate and material is reduced, equipment investment is reduced, production cost is saved, productivity is improved, and competitiveness of the display device is increased, while the transmittance requirement is met.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: December 6, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Feng Zhang, Qi Yao, Zhiyong Liu
  • Patent number: 9515103
    Abstract: A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate (1) and depositing a buffer layer (2); Step 2: depositing an a-Si layer (3); Step 3: depositing and patterning a silicon oxide layer (4); Step 4: taking the silicon oxide layer (4) as a photomask and annealing the a-Si layer (3) with excimer laser, so that the a-Si layer crystallizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region (31) and a second poly-Si region (32); Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions (31) and (32), and forming an LDD area; Step 7: depositing and patterning a gate insulating layer (5); Step 8: forming a first gate (61) and a second gate (62); Step 9: forming via holes (70); and Step 10: forming a first source/drain (81) and a second source/drain (82).
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: December 6, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Gaiping Lu
  • Patent number: 9508787
    Abstract: Two rows of resistive bodies, first resistive body and second resistive body, having slits are provided on an input matching circuit substrate. Since a high-frequency signal flows through not only the resistive bodies but also a transmission line pattern formed in the slits, the burnout of the resistive bodies can be prevented.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: November 29, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takaaki Yoshioka
  • Patent number: 9502243
    Abstract: A method of forming a semiconductor device that includes providing a base semiconductor substrate having a first orientation crystal plane, and forming an epitaxial oxide layer on the base semiconductor substrate. The epitaxial oxide layer has the first orientation crystal plane. A first semiconductor layer having a second orientation crystal plane is then bonded to the epitaxial oxide layer. A portion of the first semiconductor layer is removed to expose a second surface of the epitaxial oxide layer. A remaining portion of the first semiconductor layer is present on the first surface of the epitaxial oxide layer; and epitaxially forming a second semiconductor layer on the second surface of the epitaxial oxide layer, wherein the second semiconductor layer has a first orientation crystal plane.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: November 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9502686
    Abstract: Methods for forming an OLED device are described. An encapsulation structure having organic buffer layer and an interface layer disposed on the organic buffer layer sandwiched between barrier layers is deposited over an OLED structure. In one example, the method includes depositing a first barrier layer on a region of a substrate having an OLED structure disposed thereon, depositing a buffer layer with a fluorine-containing plasma formed from a first gas mixture containing a polymer gas precursor and a fluorine containing gas on the first barrier layer, depositing an interface layer on the buffer layer with a second gas mixture containing the polymer gas precursor, and depositing a second barrier layer on the interface layer.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: November 22, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jrjyan Jerry Chen, Soo Young Choi
  • Patent number: 9496384
    Abstract: The present invention provides a semiconductor device that can achieve both low on-resistance and high withstand voltage, while reducing the device size, improving the manufacturing yield, and reducing the cost. The semiconductor device 1 includes a substrate 5, an epitaxial layer 6 formed on the substrate 5 and formed with a gate trench 11, a gate insulating film 17 formed on the side surface 14 and the bottom surface 15 of the gate trench 11, a gate electrode 20 embedded in the gate trench 11 and opposed to the epitaxial layer 6 with the gate insulating film 17 therebetween, and a source layer 25, a channel layer 26, and a drift layer 27 formed in this order from a first surface to a second surface of the epitaxial layer 6, in which the on-resistance Ron represented by a variable “y” and the withstand voltage Vb represented by a variable “x” functionally satisfy the following relational expression (1): y?9×10?7x2?0.0004x+0.7001??(1).
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: November 15, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Patent number: 9484454
    Abstract: A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: November 1, 2016
    Assignee: Tower Semiconductor Ltd.
    Inventors: Sagy Levy, Sharon Levin, Noel Berkovitch
  • Patent number: 9478489
    Abstract: The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Daniel Richter, Frank Kuechenmeister
  • Patent number: 9470652
    Abstract: A sensing device includes a sensor die having a sensing region formed at a first surface of the sensor die. The sensing device further includes an encapsulant covering the sensing die, the encapsulant having a cavity formed therein, wherein the cavity exposes the sensing region. A sensitive membrane material is deposited within the cavity over the sensing region. A method of manufacturing sensing devices entails mounting a plurality of sensing dies to a carrier, encapsulating the dies in an encapsulant, forming cavities in the encapsulant, the cavities exposing a sensing region of each sensor die, and depositing the sensitive membrane material within each of the cavities. The encapsulating and forming operations can be performed simultaneously using a film-assisted molding (FAM) process, and the depositing operation is performed following FAM at an ambient temperature that is lower than the temperature needed to perform FAM.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: October 18, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Stephen R. Hooper, Leo M. Higgins, III, Raymond M. Roop
  • Patent number: 9466610
    Abstract: Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around (GAA) vertical gate (VG) semiconductor structure comprising providing a substrate; forming a plurality of layers having alternating first insulative material layers and second insulative material layers over the substrate; identifying bit line and word line locations for the formation of bit lines and word lines; removing at least a portion of the plurality of layers outside of the identified bit line and word line locations, each of the removed portions extending through the plurality of layers to at least a top surface of the substrate; forming a vertical first insulative material structure in the removed portions; performing an isotropic etching process to remove the second insulative material from the second insulative material layers; forming bit lines in the second insulative material layers within the identified bit line locations; and forming word lines in the identified word line locations.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: October 11, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Ta-Hone Yang
  • Patent number: 9466649
    Abstract: An organic light emitting diode display is provided including: a substrate including a display area and a non-display area positioned at a circumference of the display area; a thin film transistor formed on the substrate; a first electrode formed on the thin film transistor and electrically connected to the thin film transistor; a pixel definition layer formed on the first electrode and defining a pixel area; and an emission layer formed on the first electrode and contacting the first electrode in the pixel area, wherein the display area is divided into a first region, and a second region including a remainder of the display area except for the first region, and a cross-sectional area ratio of the pixel definition layer that a cross-section of the pixel definition layer occupies for a unit pixel is different in the first region and the second region.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: October 11, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Kyung Hyun Choi
  • Patent number: 9461037
    Abstract: A structure and method for reducing second-order harmonic distortion in FET devices used in applications that are sensitive to such distortion, such as switching RF signals. The asymmetry of the drain-to-body capacitance Cdb and source-to-body capacitance Csb of a FET device are equalized by adding offsetting capacitance or a compensating voltage source.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: October 4, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Alper Genc