Abstract: A method of forming a dielectric film including a zirconium oxide film includes: forming a zirconium oxide film on a substrate to be processed by supplying a zirconium material and an oxidant, the zirconium material including a Zr compound which includes a cyclopentadienyl ring in a structure, and forming a titanium oxide film on the zirconium oxide film by supplying a titanium material and an oxidant, the titanium material including a Ti compound which includes a cyclopentadienyl ring in a structure.

Abstract: There is provided a semiconductor light emitting device and method of making the same, having a first conductivity type semiconductor layer; an active layer formed on the first conductivity type semiconductor layer; a second conductivity type semiconductor layer formed on the active layer and including a plurality of holes; and a transparent electrode formed on the second conductivity type semiconductor layer.

Abstract: A light-emitting diode has a metal structure, a light-emitting chip, and a bowl structure. The metal structure has a platform and a heat sink. The platform has a top face, a first side, and a second side opposite to the first side. A first reflector and a second reflector respectively extend from the first side and the second side. The heat sink extends below the top face and has a drop from the bottom surfaces of the first reflector and the second reflector. The light-emitting chip is disposed on the top face. The bowl structure covers the outer surface of the metal structure and shields the bottom surfaces of the first reflector and the second reflector. A thermal dispassion surface of the heat sink is exposed from the bowl structure. An inner surface of bowl wall has a plurality of reflection structures to promote the light extraction efficiency.

Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.

Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together.

Abstract: A light emitting diode (LED) package structure including a leadframe, a housing, a LED chip and a light-transmissive encapsulant is provided. The leadframe has a first electrode and a second electrode separated from each other. The housing wraps the first electrode and the second electrode and includes a recess having a bottom and a sidewall. The bottom of the recess has a cover layer covering the leadframe and having an opening exposing an end of the first electrode, an end of the second electrode and a spacer disposed therebetween and connected thereto wherein the spacer, the end of the first electrode and the end of the second electrode are substantially coplanar. The LED chip is disposed in the recess and electrically connected to leadframe. The light-transmissive encapsulant is filled in the recess.

Abstract: A flat panel display having a thin-film transistor (TFT) and a pixel unit and a method of manufacturing the same are disclosed. In one embodiment, the method includes forming a step difference layer having a relatively high step and a relatively low step on a substrate and forming an amorphous silicon layer on the step difference layer along a height shape of the step difference layer. The method further includes crystallizing the amorphous silicon layer into a crystalline silicon layer and polishing the crystalline silicon layer to form a planarized surface of the crystalline silicon layer having no height differences so that the crystalline silicon layer remains on a region corresponding to the low step and an active layer is formed. According to this method, crystallization protrusions are effectively removed from the active layer, and thus, stable brightness characteristics of the display apparatus are guaranteed.

Abstract: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.

Abstract: Through substrate via barrier structures and methods are disclosed. In one embodiment, a semiconductor device includes a first substrate including an active device region disposed within isolation regions. A through substrate via is disposed adjacent to the active device region and within the first substrate. A buffer layer is disposed around at least a portion of the through substrate via, wherein the buffer layer is disposed between the isolation regions and the through substrate via.

Abstract: A semiconductor device includes a silicon substrate having a protrusion, a gate insulating film formed over an upper surface of the protrusion of the silicon substrate, a gate electrode formed over the gate insulating film, a source/drain region formed in the silicon substrate on the side of the gate electrode, a first side wall formed over the side surface of the protrusion of the silicon substrate, the first side wall containing an insulating material, a second side wall formed over the first side wall, the second side wall having a bottom portion formed below the upper surface of the protrusion of the silicon substrate, the second side wall containing a material having a Young's modulus greater than that of the silicon substrate, and a stress film formed over the gate electrode and the second side wall.

Abstract: A semiconductor package includes a substrate including a substrate body having a first face and a second face opposing the first face. A first through electrode passes through the substrate body between the first face and the second face. An insulation member is disposed over the first face; and a connection member having a first conductive unit disposed inside of the insulation member is electrically connected to the first through electrode, and a second conductive unit electrically connected to the first conductive unit is exposed at side faces of the insulation member. A semiconductor chip having third and fourth faces is disposed over the first face of the substrate body in a vertical direction. A second through electrode passes through the substrate body between the third and fourth faces and is electrically connected to the second conductive unit.

Abstract: A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions.

Abstract: A high-voltage oxide transistor includes a substrate; a channel layer disposed on the substrate; a gate electrode disposed on the substrate to correspond to the channel layer; a source contacting a first side of the channel layer; and a drain contacting a second side of the channel layer, wherein the channel layer includes a plurality of oxide layers, and none of the plurality of oxide layers include silicon. The gate electrode may be disposed on or under the channel layer. Otherwise, the gate electrodes may be disposed respectively on and under the channel layer.

Abstract: A blue color photoelectric conversion film includes: a p-type layer formed by depositing tetracene; a p,n-type layer formed by co-depositing tetracene and naphthalene-tetracarboxylic-dianhydride (“NTCDA”) on the p-type layer; and an n-type layer formed by depositing NTCDA on the p,n-type layer.

Abstract: Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays.

Abstract: A process for producing a semiconductor device comprises the following process steps: provision of a semiconductor substrate (1); formation of a functional layer (2) on a semiconductor surface (11) of the semiconductor substrate (1); and production of at least one doped section (3) on the semiconductor surface (11) by driving a dopant into the semiconductor substrate (1) from the functional layer (2). The functional layer (2) is formed in such a way that it passivates the semiconductor surface (11), acting as a passivation layer upon completion of the semiconductor device.

Abstract: A conductive electrode paste or ink formulation including a getter removes or reduces the concentration of the unwanted impurities in an electronic device. These reductions may happen during or immediately after the fabrication or sealing of the device, or they may occur after some activation time or event. Water, oxygen, carbon dioxide, hydrogen, and residual solvents are gettered.

Abstract: A semiconductor device having a semiconductor die is provided. The semiconductor die includes a main horizontal surface, an outer edge, an active area, and a peripheral area. The peripheral area includes a dielectric structure surrounding the active area and extending from the main horizontal surface into the semiconductor die. The dielectric structure includes, in a horizontal cross-section, at least one substantially L-shaped portion that is inclined against the outer edge. Further, a method for forming a semiconductor device is provided.

Abstract: Microelectronic structures and devices, and method of fabricating a three-dimensional microelectronic structure is provided, comprising passing a first precursor material for a selected three-dimensional microelectronic structure into a reaction chamber at temperatures sufficient to maintain said precursor material in a predominantly gaseous state; maintaining said reaction chamber under sufficient pressures to enhance formation of a first portion of said three-dimensional microelectronic structure; applying an electric field between an electrode and said microelectronic structure at a desired point under conditions whereat said first portion of a selected three-dimensional microelectronic structure is formed from said first precursor material; positionally adjusting either said formed three-dimensional microelectronic structure or said electrode whereby further controlled growth of said three-dimensional microelectronic structure occurs; passing a second precursor material for a selected three-dimensional mi

Abstract: The present invention provides systems, methods and apparatus for manufacturing a memory cell. The invention includes forming a feature having sidewalls in a first dielectric material; forming a first conductive material on the sidewalls of the feature; depositing a layer of a second dielectric material on the conductive material; and exposing the second dielectric material to oxidizing species and ultraviolet light to oxidize the second dielectric material. Numerous additional aspects are disclosed.