Abstract: The invention relates to a device for synchronizing a periodic high frequency power signal (18) and an external reference signal (10). The device comprises a phase control circuit (100) and a digital oscillator circuit (130). The digital oscillator circuit (130) is connected to the phase control circuit (100). The digital oscillator circuit (130) comprises means for generating the periodic high frequency power signal (18) dependent on the control signal from the phase control circuit. The phase control circuit (100) is configured to determine a phase difference of the periodic high frequency power signal (18) and the external reference signal (10).

Abstract: A disclosed apparatus for accomplishing such a task may include (1) a circuit board incorporated into a module designed for insertion into slots of computing devices, (2) at least one conductive contact disposed on the circuit board, (3) a counter circuit disposed on the circuit board and communicatively coupled to the conductive contact, wherein the counter circuit comprises (A) a signal-change detector that detects signal changes as the module is inserted into one of the slots of the computing devices and (B) a counter device that maintains a dynamic count indicative of a number of times that the module has been inserted into one of the slots of the computing devices based at least in part on the signal changes, (4) a battery electrically coupled to the counter circuit, wherein the battery powers the counter device prior to the insertion. Various other apparatuses, systems, and methods are also disclosed.

Abstract: Methods and systems for generating a product packaging model for a product offering of a set of product items associated with a merchant account. At an e-commerce platform, a trigger event is detected and, in response, two or more product items are automatically selected to form a kit that makes up the product offering. Model data for the two or more product items and packaging parameters are used to automatically select a packaging option and to build a product packaging model that is sent to the merchant account. The product packaging model may be a three-dimensional computer model of the kit containing the two or more product items.

Abstract: A hybrid quantum classical (HQC) computer, which includes both a classical computer component and a quantum computer component, implements improvements to the quantum approximate optimization algorithm (QAOA) which enable QAOA to be applied to valuable problem instances (e.g., those including several thousand or more qubits) using near-term quantum computers.

Abstract: A system and corresponding method that achieves coherency and deterministic latency (CDL) autonomously upon power on is disclosed. The system, for example, a multi-channel RF system, may require CDL with respect to the digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) assigned to the channels in the system. CDL is achieved through a timed combination of external reference and synchronization signals, resetting and disabling of various clock dividers, and enabling clock generation. In addition to synchronizing all of the clocks, the data acquisition sequence must be synchronized across all of the channels, whether they are on chips, cards, or chassis. Data acquisition synchronization may be implemented using an initiator/target or a wired OR mode configuration.

Abstract: Methods and systems are described for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote measurements, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.

Abstract: A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.

Abstract: In one embodiment, a local clock is synchronized to a master clock using a Kalman filter to determine state variables using a state transition matrix that includes at least one coefficient that is associated with a digital-to-analog converter (DAC), where the state variables include a unit step variable indicative of a unit step for the system. The local clock is controlled based on the state variables determined using the Kalman filter. The unit step is indicative of an amount by which the frequency of the local clock signal changes in response to a change in the digital input of the DAC.

Abstract: A dynamic aperture is disclosed. A dynamic aperture includes a base layer, a conductive structure disposed on the base layer, and a layer of a material having a dynamically controllable electrical conductivity that is disposed over the base layer and the conductive structure. A transmission profile of the dynamic aperture is determined by a combination of the conductive structure and the layer of the material. The transmission profile is dynamically alterable by controlling the electrical conductivity of the layer of the material.

Abstract: A product-sum operation device includes a product operator and a sum operator. The product operator includes a plurality of variable-input product operation elements and a plurality of fixed-input product operation elements. Each of the plurality of variable-input product operation elements and the plurality of fixed-input product operation elements and is a resistance change element. The product-sum operation device includes variable input units and that input a variable signal to a plurality of variable-input product operation elements and fixed input units and that input a determined signal to the plurality of fixed-input product operation elements and in synchronization with the variable signal. The sum operator includes an output detector that determines the sum of outputs from the plurality of variable-input product operation elements and outputs from the plurality of fixed-input product operation elements.

Abstract: Methods and systems for controlling a multipurpose power converter for converting power for a transport climate control system are provided. The multipurpose power converter includes a rectifier having a first leg, a second leg, and a third leg. The multipurpose power converter also includes a first switch, a second switch, and an inductor-capacitor network. The first switch and the second switch are connected to the third leg. The inductor-capacitor network is connected to the first switch. When the first switch is on and the second switch is off, the multipurpose power converter is configured as a single-phase AC power converter. When the first switch is off and the second switch is on, the multipurpose power converter is configured as a three-phase AC power converter.

Abstract: A semiconductor switch device includes a switchable power semiconductor and a control circuit. The semiconductor switch device has a current sink and a current amplifier designed to amplify during a switching process a partial current of the total current flowing across the control capacitor that is not discharged by the current sink up to an adjustable maximum current and to apply the amplified partial current to the control electrode of the power semiconductor so as to counteract the change in the voltage across the collector-emitter path or the drain-source path of the power semiconductor during the switching process. An additional circuit provides an adapted switch-on transition by smoothing the collector voltage and/or the drain voltage of the switchable power semiconductor when switching over the collector-emitter path or the drain-source path of the power semiconductor from a blocked state into a conductive state.

Abstract: A window type watchdog timer includes a frequency dividing circuit for generating a frequency-divided clock signal by dividing a frequency of a reference clock signal; a monitoring circuit for monitoring occurrence of a first error in which clear control from a target device is interrupted for a first time or more, and occurrence of a second error in which an interval between two consecutive clear controls from the target device is shorter than a second time shorter than the first time, based on the frequency-divided clock signal; and outputting an error signal when the first error or the second error is detected; and a setting circuit for variably setting the first time and the second time by variably setting a frequency division ratio in the frequency dividing circuit and variably setting a detection condition of the first error and the second error.

Abstract: The invention relates to a method for determining a time of a flank in a signal, wherein the method comprises a step of reading the signal and has a master clock rate for operating a digital evaluation unit for evaluating the time of the flank. The method also comprises a step of forming a data word representing the signal, using a deserializer of a SERDES cell, wherein the data word has a plurality of bits, and wherein a sampling clock rate is applied to the SERDES cell for sampling the signal, which sampling clock rate is higher than the master clock rate, wherein one flank or two flanks of the sampling clock rate are used for sampling the signal. Finally, the method comprises a step of determining the time of the flank in the signal using the data word and the master clock rate in the evaluation unit.

Abstract: A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

Abstract: A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

Abstract: A DLL circuit that has a programmable output frequency is provided. In various embodiments, the DLL circuit comprises an input configured to receive an input clock defining an input clock period; an output configured to provide a DLL output clock; a delay line configured to receive the input clock, wherein the delay line comprises a plurality of delay stages, each configured to generate one of a plurality of delay line output clocks, each of the delay line output clocks having a phase relative to the input clock based on a delay of the delay line; a clock generation circuit, configured to generate the DLL output clock based on a selected plurality of the delay line output clocks; and a control circuit configured to select which of the delay line output clocks the clock generation circuit uses to generate the DLL output clock.

Abstract: Systems and methods for monitoring poultry house egg production. The system includes: a conveyor for conveying poultry eggs; at least one laser sensor directed in direction of said conveyor for measuring distance of said conveyor's surface and poultry eggs conveyed thereupon; a computer coupled with said at least one lase sensor; wherein, number of poultry eggs passed through said conveyor at a given moment is determined by identifying and analyzing fluctuations in measured distance from said at least one laser sensor.

Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

Abstract: Gate drivers and auto-zero comparators are disclosed. An example integrated circuit includes a transistor comprising a gate terminal and a current terminal, a gallium nitride (GaN) gate driver coupled to the gate terminal, the GaN gate driver configured to adjust operation of the transistor, and an enhancement mode GaN comparator coupled to at least one of the transistor the GaN gate driver, the enhancement mode GaN comparator configured to compare a voltage to a reference voltage, the voltage based on current from the current terminal, the GaN gate driver configured to adjust the operation of the transistor based on the comparison.