Abstract: A content transmitting apparatus, includes: an acquisition device configured to acquire content data distributed in streaming mode; a temporary storage device configured to store temporarily the content data acquired by the acquisition device; a data control device configured to read the content data from the temporary storage device on a first-in first-out basis; an encryption device configured to encrypt in units of a predetermined amount the content data read out by the data control device; and a transmission device configured to transmit the content data encrypted by the encryption device to a predetermined receiving apparatus via a network. If the remaining capacity of the temporary storage device becomes smaller than a predetermined threshold value depending on status of the network, then the data control device discards the content data read from the temporary storage device.

Abstract: A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.

Abstract: Embodiments of the present invention provide a method and system, in a network storage system, for producing a balanced reconstruction load across storage devices (disks) in a storage array (array) using a scalable declustered layout. A scalable declustered layout is a logical configuration of parity groups across storage units (disk segments) which spread the chunk load and total share load of parity groups across disks in the array. Creation of a scalable declustered layout is achieved by sequentially selecting and allocating each chunk of a new (prospective) parity group according to the then-current load on each disk. The scalable declustered layout is then implemented on the disks to produce a balanced reconstruction load across disks when recovering from a disk failure.

Abstract: A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element.

Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Abstract: A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.

Abstract: Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.

Abstract: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

Abstract: A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having a different voltage level depending on a normal mode or a self-refresh mode in response to the voltage level selection signals.

Abstract: A semiconductor device includes a BIST circuit configured to detect a defective bit in a DRAM connected to the semiconductor device, and retrieve an address of the detected defective bit, a non-volatile eFuse macro configured to retain the address of the defective bit in the DRAM, the defective bit being detected by the BIST circuit, and a repair register configured to store data for the address of the defective bit. The semiconductor device also includes an address controller configured to, based on the address retained in the eFuse macro, perform control to use the repair register during writing or reading of data to or from the address of the defective bit.

Abstract: Channel coupling effects during verify and read of non-volatile storage are mitigated by matching the amount of channel coupling that occurs during read with channel coupling that occurred during verify. All bit lines may be read together during both verify and read. In one embodiment, first bias conditions are established on bit lines when verifying each of a plurality of programmed states. A separate set of first bias conditions may be established when verifying each state. Biasing a bit line may be based on the state to which a non-volatile storage elements on the bit line is being programmed. A separate set of second bias conditions are established for each state being read. The second bias conditions for a given state substantially match the first bias conditions for the given state.

Abstract: A semiconductor memory device that includes a supply voltage pad, a ground voltage pad, and at least two data input/output pads arranged between the supply voltage pad and the ground voltage pad. The semiconductor memory device has a first pull-up driver that is connected to the second data input/output pad located at a first distance from the supply voltage pad, and a first pull-down driver that is connected to the first data input/output pad located at a second distance from the ground voltage pad.

Abstract: An output current of a memory cell is sensed by a sensing circuit for distinguishing a program state and an erase state of the memory cell. The sensing circuit includes a reference transistor, a P-type MOSFET, and an N-type MOSFET. The P-type MOSFET has a gate connected to a memory cell for receiving an output current of the memory cell. The N-type MOSFET has a drain connected to a drain of the first P-type MOSFET, and has a source connected to ground. The inverter has an input terminal connected to the drain of the first N-type MOSFET. The voltage at an output terminal of the inverter is used for indicating the program state or the erase state of the memory cell. The reference transistor has a gate connected to a reference signal, and has a drain connected to the gate of the P-type MOSFET.

Abstract: Methods for reading a memory cell are provided. The method for reading a memory cell includes applying a first read pulse to a memory cell, heating the memory cell to a first temperature and obtaining a first read data. The first read data is converted to a first digital data. The first digital data is stored in a shift register. A second read pulse is applied to the memory cell, heating the memory cell to a second temperature and obtaining a second read data. The second read data is converted to a second digital data. The second digital data is stored in the shift register. A ratio of the first digital data and the second digital data is calculated, obtaining a quotient. The quotient is converted to an analog value. A log amplifier circuit takes the log of the analog value, representing an activation energy state.

Abstract: A machine implemented process and system is provided. The process determines if any right granted to an entity for performing an I/O operation associated with a data container stored at a first storage volume is to be revoked. The right itself may be cached at the first storage volume and resident at a second storage volume. A recall message is sent to the node that manages the second storage volume. Any pending I/O operation is completed, after the message is sent and before the right is revoked. Thereafter, the right is revoked and the cached copies of the right are invalidated.

Abstract: A resistive memory cell that includes a metal-polymer bi-layer proximate a CMOS gate. The memory cell has a substrate having a source contact connected to a source line and a drain contact connected to a drain line, a CMOS gate proximate the substrate electrically connecting the source contact and the drain contact, the bi-layer adjacent the CMOS gate, the bi-layer comprising a thin metal layer and a polymer layer, and a word line connected to the bi-layer.

Abstract: A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate, a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, an emitter contact layer disposed in a second side of the semiconductor substrate, and a base layer separating the plurality of collector contacts from the emitter contact layer. Each collector contact is electrically isolated from each other. A resistive sense memory cells is electrically coupled to each collector contacts and a bit line. The base layer and the emitter contact layer provide an electrical path for the plurality of collector contacts.

Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Abstract: The present invention discloses a decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage. The present invention further discloses a method of implementing the decoding circuit and a memory circuit using the decoding circuit.

Abstract: A first interconnect card is configured, wherein a first controller is included in the first interconnect card. A second interconnect card coupled to the first interconnect card is configured, wherein a second controller is included in the second interconnect card. In response to a failure of the first controller included in the first interconnect card, the first interconnect card is controlled via the second controller included in the second interconnect card. In response to a failure of the second controller included in the second interconnect card, the second interconnect card is controlled via the first controller included in the first interconnect card.