Patents Examined by Hau H. Nguyen
  • Patent number: 7916147
    Abstract: A centralised game server in a bank (50) of game servers runs a game program for use by a user at a remote terminal (52, 56, 58). In the game server, the game program sends a first set of graphics instructions to a first graphics processing unit (76) which is intercepted by an instruction interception module (74). The first set of instructions, including vertex data, transformation data and texture data are passed to the first graphics processing unit (76) whilst a specially manipulated version of the instructions is generated and passed to a second graphics processing unit (78). The first graphics processing unit (76) renders the image data as the game intended whilst the second graphics processing unit (78) is used to render specially adapted graphics data from which to extract compression assistance data used for compression, e.g. motion vectors.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: March 29, 2011
    Assignee: T5 Labs Ltd.
    Inventors: Graham Clemie, Dedrick Duckett
  • Patent number: 7903121
    Abstract: A system and method for rendering with an object proxy. In one embodiment, a method includes forming a set of view textures corresponding to a set of viewing directions; selecting a viewing direction for rendering; selecting at least two view textures from the formed set based on the selected viewing direction; and rendering the object proxy at the selected viewing direction. The rendering step includes applying texture from the selected view textures onto the selected object proxy. The view texture set forming step includes: calculating texture coordinates for the object proxy based on the level of obstruction at different portions of the object proxy and texture packing data; and drawing portions of the object based on the level of obstruction data for the object proxy and based on the texture packing data to obtain a view texture at the selected viewing direction.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: March 8, 2011
    Assignee: Graphics Properties Holdings, Inc.
    Inventor: Radomir Mech
  • Patent number: 7898548
    Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: March 1, 2011
    Assignee: STMicroelectronics, Inc.
    Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
  • Patent number: 7898547
    Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: March 1, 2011
    Assignee: Broadcom Corporation
    Inventors: Chun Wang, Youjing Zhang, Richard K. Sita, Glen T. McDonnell, Babs L. Carter
  • Patent number: 7898550
    Abstract: Various embodiments for reducing external bandwidth requirements for transferring graphics data are included. One embodiment includes a system for reducing the external bandwidth requirements for transferring graphics data comprising a prediction error calculator configured to generate a prediction error matrix for a pixel tile of z-coordinate data, a bit length calculator configured to calculate the number of bits needed to store the prediction error matrix, a data encoder configured to encode the prediction error matrix into a compressed block and a packer configured to shift the compressed block in a single operation to an external memory location.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: March 1, 2011
    Assignee: VIA Technologies, Inc.
    Inventors: Boris Prokopenko, Timou Paltashev
  • Patent number: 7898549
    Abstract: A graphics processing subsystem defines a bounding area as the portion of the display buffer and other memory buffers occupied by one or more rendered objects. When clearing the memory buffers, only the portions of the buffers corresponding to the bounding area need to be cleared. A graphics pipeline includes a bounding area memory to store bounding area values. The bounding area values are modified during rendering so that each rendered primitive falls within the bounding area values. The graphics processing subsystem clears a portion of the memory buffer in response to a clear command specifying a bounding area. The clear command may include a set of bounding area values defining the bounding area, or alternatively a reference to the bounding area memory. For applications that draw objects in isolation, the bounding area will be smaller than the window, resulting in a decreased time requirement for clearing the memory buffer.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: March 1, 2011
    Assignee: NVIDIA Corporation
    Inventors: Ross A. Cunniff, Matthew J. Craighead
  • Patent number: 7893943
    Abstract: A system and method for converting a pixel rate of a digital image frame is provided. The system includes a display controller with an embedded buffer and programmable input and output buffers. The input buffer writes lines of the frame at a source pixel rate while the output pointer reads out lines of the frame at a display pixel rate thereby allowing display of an image having a source pixel rate that is different, e.g., higher, than a display pixel rate.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: February 22, 2011
    Assignee: Pixelworks, Inc.
    Inventor: Michael G. West
  • Patent number: 7893941
    Abstract: Methods and apparatus are provided for efficiently and intelligently communicating characteristic information in video graphics switcher environments. An intelligent video graphics switcher obtains display device characteristic information associated with multiple display devices and maintains updated characteristic information. When an event such as a connection/disconnection or switching event occurs between the video graphics switcher and a display device, the characteristic information is communicated to an appropriate host by triggering a connection/disconnection event with the host.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: February 22, 2011
    Assignee: RGB Spectrum
    Inventors: Don Day, David Haycock
  • Patent number: 7884830
    Abstract: A graphics system supports arrays of cube map textures. In one implementation, a cube map texture is utilized as an index into a set of cube map textures. The set of cube map textures may further be arranged into an atlas of two-dimensional textures.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: February 8, 2011
    Assignee: Nvidia Corporation
    Inventors: Simon G. Green, Mark J. Harris, Oliver Strunk
  • Patent number: 7880745
    Abstract: Systems and methods for border color handling in a graphics processing unit are disclosed. In one embodiment, the system includes a border color register that stores at least one border color pointer. A border color pointer indicates an address in an external memory at which border color information is located. Border color information is populated within external memory and retrieved by the texture cache controller if the texture filter unit requires a border color for texture mapping operations.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: February 1, 2011
    Assignee: Via Technologies, Inc.
    Inventors: Jim Xu, Mike Hong, John Brothers
  • Patent number: 7880742
    Abstract: An information processing device in which a data bus for establishing interconnection between a plurality of control operating units formed in a main processor is connected at one end to a graphic processor and at the other end to a main memory. Image frame data generated by the graphic processor is sequentially transferred through the data bus and stored into the main memory. The data bus satisfies R1?R2?R4 and R1?R3?R4, where R1 is the data transmission rate from the main processor to the graphic processor, R2 is the data transmission rate from the graphic processor to the main processor, R3 is the data transmission rate between the main processor and the main memory, and R4 is the rate to transmit a single image frame of data within a vertical blanking interval.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: February 1, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Katsu Saito
  • Patent number: 7876327
    Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: January 25, 2011
    Assignee: NVIDIA Corporation
    Inventors: Krishnan Sreenivas, Koen Bennebroek, Sanford S. Lum, Karthik Bhat, Stefano A. Pescador, David G. Reed, Brad W. Simeral, Edward M. Veeser
  • Patent number: 7876328
    Abstract: Provided is a system for managing multiple contexts in a decentralized graphics processing unit. The system includes multiple control units that can include a context buffer, a context processor, and a context scheduler. Also included is logic to receive multiple contexts, logic to identify at least one of the contexts, and logic to facilitate communication among the control units.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: January 25, 2011
    Assignee: Via Technologies, Inc.
    Inventors: Qunfeng (Fred) Liao, Yang (Jeff) Jiao, Yijung Su
  • Patent number: 7868897
    Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: January 11, 2011
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Aditya Navale, Wishwesh A. Gandhi
  • Patent number: 7859542
    Abstract: A method for synchronizing two of more graphics processing units. The method includes the steps of determining whether the phase of a first timing signal of a first graphics processing unit and the phase of a second timing signal of a second graphics processing unit are synchronized, and adjusting the frequency of the first timing signal to the frequency of the second timing signal if the first timing signal and the second timing signal are not synchronized.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: December 28, 2010
    Assignee: NVIDIA Corporation
    Inventors: Ian M. Williams, Dat T. Nguyen, Jeffrey Chandler Doughty, Ralf Biermann, Kenneth Leon Adams, Jr., Andrew B. Ritger, Satish D. Salian, Fred D. Nicklisch
  • Patent number: 7852344
    Abstract: An apparatus comprising a memory and a coder/decoder circuit. The memory may have a first memory portion and a second memory portion. The coder/decoder circuit may be configured to (i) position a set of atoms across the memory, (ii) define a strip across a portion of the atoms, (iii) designate a first atom within the strip, (iv) locate one or more second atoms to be paired with the first atom, (v) determine whether the one or more second atoms when paired with the first atom forms a legitimate pair, and (vi) read the legitimate pair from the first memory portion and the second memory portion.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: December 14, 2010
    Assignee: LSI Corporation
    Inventors: Adrian Philip Wise, James A. Darnes
  • Patent number: 7847801
    Abstract: A computer implemented method, apparatus, and computer usable program code are provided for managing dual active controllers in a high availability storage configuration. Redundant dual active controllers in high availability storage configurations are made to appear as individual storage target devices to a host system. Each controller owns certain volumes of data storage. When a host system sends a request to identify available data volumes, the controller that owns certain volumes provides preferred paths to those owned volumes. The host system may also send an inquiry to a controller that asks the controller about data volumes not owned by the controller. For such inquiries, no paths to the non-owned data volumes are returned to the host system.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: December 7, 2010
    Assignee: LSI Corporation
    Inventor: Yanling Qi
  • Patent number: 7843457
    Abstract: A PC-based computing system employing a bridge chip with a routing unit to distribute geometrical data and graphics commands to multiple GPU-driven pipeline cores supported on a plurality of graphics cards and the bridge chip. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU) supported on a motherboard, for executing the OS, graphics applications, drivers and graphics libraries. The routing unit in the bridge chip interfaces with the CPU and the GPU-driven pipeline cores.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: November 30, 2010
    Assignee: Lucid Information Technology, Ltd.
    Inventors: Reuven Bakalash, Offir Remez, Efi Fogel
  • Patent number: 7834880
    Abstract: A high performance graphics processing and display system architecture supporting a cluster of multiple cores of graphic processing units (GPUs) that cooperate to provide a powerful and highly scalable visualization solution supporting photo-realistic graphics capabilities for diverse applications. The present invention eliminates rendering bottlenecks along the graphics pipeline by dynamically managing various parallel rendering techniques and enabling adaptive handling of diverse graphics applications.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: November 16, 2010
    Assignee: Lucid Information Technology, Ltd.
    Inventors: Reuven Bakalash, Offir Remez, Efi Fogel
  • Patent number: RE41967
    Abstract: A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: November 30, 2010
    Inventors: Takatoshi Ishii, Edmund Cheung, Sherwood Brannon