Abstract: A texture processing pipeline in a graphics processing unit generates the surface appearance for objects in a computer-generated scene. This texture processing pipeline determines, at multiple stages within the texture processing pipeline, whether texture operations and texture loads may be processed at an accelerated rate. At each stage that includes a decision point, the texture processing pipeline assumes that the current texture operation or texture load can be accelerated unless specific, known information indicates that the texture operation or texture load cannot be accelerated. As a result, the texture processing pipeline increases the number of texture operations and texture loads that are accelerated relative to the number of texture operations and texture loads that are not accelerated.

Abstract: According to an embodiment, an electronic device may include at least one processor, a display, a memory configured to store image frames, and a display controller configured to output the image frames. The at least one processor may be configured to transmit a first image frame to be output through the display, based on a first timing signal received from the display controller, identify a state of the electronic device, transmit first control information for changing a timing of the first timing signal, in response to transmitting the first control information for changing the timing of the first timing signal, receive a second timing signal from the display controller, and transmit, to the memory, a second image frame to be output through the display, based on the received second timing signal. The timing of the second timing signal may differ from the timing of the first timing signal.

Abstract: Methods, apparatus, and computer readable storage medium for simulating and rendering a material with a modified material point method are described. The method includes, for each of a plurality of time-steps of simulating a material: transferring states of particles representing the material at a N-th time-step to a grid, determining a plurality of grid-node velocities at the N-th time-step using a particle-to-grid computation based on the states of the particles at the N-th time-step, updating the plurality of grid-node velocities at a (N+1)-th time-step based on grid forces, and updating the states of the particles at the (N+1)-th time-step using a grid-to-particle computation based on the states of the particles at the N-th time-step, the plurality of grid-node velocities at the N-th and (N+1)-th time-steps. The method further includes rendering one or more image depicting the material based on the states of the particles at the plurality of time-steps.

Abstract: A system for three dimensional (3D) model texturing. The system includes a computing device configured to: instruct a camera to capture images of an object; construct a 3D model of the object based on the images; texture the 3D model using keyframes of the images to obtain a textured 3D model; generate guidance images by projecting the textured 3D model to camera poses of the keyframes; for each guidance image and keyframe pair: modify the guidance image and the keyframe based on their correspondence to obtain enhanced guidance image and warped image, combine the enhanced guidance image and the warped image to obtain harmonized image, and project color from the harmonized images to the 3D model to obtain textured 3D model.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: Embodiments of this application disclose methods, systems, and devices for video synthesis. In one aspect, a method comprises obtaining a plurality of frames corresponding to source image information of a first to-be-synthesized video, each frame of the source image information. The method also comprises obtaining a plurality of frames corresponding to target image information of a second to-be-synthesized video. For each frame of the plurality of frames corresponding to the target image information of the second to-be-synthesized video, the method comprises fusing a respective source image from the first to-be-synthesized video, a corresponding source motion key point, and a respective target motion key point corresponding to the frame using a pre-trained video synthesis model, and generating a respective output image in accordance with the fusing. The method further comprises repeating the fusing and the generating steps for the second to-be-synthesized video to produce a synthesized video.

Abstract: Disclosed herein a method of removing a point cloud outlier and an apparatus implementing the method. The method includes: arranging a point cloud obtained from a laser scanner along at least a first direction; selecting, neighboring first-axis points, between which a separation degree satisfies an inspection start threshold condition, as a first leading-side representative point and a first trailing-side representative point; selecting a first leading-side outlier candidate and a first trailing-side outlier candidate based on a first leading-side separation degree and a first trailing-side separation degree; and determining the first leading-side outlier candidate and the first trailing-side outlier candidate as a first outlier point, when the number of the outlier candidates satisfies an allowable threshold condition.

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

Abstract: A graphics processing chip includes multiple graphics pipeline cores and multi-pipeline core logic circuitry to process graphic data streams received from a processor and to drive multiple GPUs on the multiple graphics pipeline cores.

Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.

Abstract: A semiconductor device includes a processor configured to perform a rendering operation of an image frame to acquire rendering data, and write the acquired rendering data on a memory device, and a display controller configured to perform a read operation of the memory device on which the rendering data is written, to acquire image data. The semiconductor device further includes a micro-sequencing circuit configured to transmit a start signal to the display controller, based on a degree of execution of the rendering operation. The display controller is further configured to, based on the transmitted start signal, start the read operation.

Abstract: A technique for performing ray tracing operations is provided. The technique includes receiving a ray for an intersection test, testing the ray against boxes specified in a bounding volume hierarchy to eliminate one or more boxes or triangles from consideration, unpacking a triangle from a compressed triangle block of the bounding volume hierarchy, the compressed triangle block including two or more triangles that share at least one vertex, and testing the ray for intersection against at least one of the unpacked triangles.

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

Abstract: Systems, methods, and media for presenting medical imaging data in an interactive virtual environment reality are provided. In some embodiments, a system comprises a head mounted display (HMD) that: determines that a transparent 3D object overlaps a 3D model of a portion of anatomy based on a medical imaging scan; sets values for pixels corresponding to portions of the 3D model not occluded by the transparent object by performing a shading operation; sets values for pixels corresponding to portions of the 3D model at the boundary of the transparent object to intensity values taken from the medical imaging data; displays the 3D model with an exterior surface shaded to evoke a 3D object, and internal surfaces at the boundaries of the transparent object not shaded to preserve details embedded in the medical imaging data.

Abstract: Apparatus and method for processing virtual graphics processor telemetry data based on quanta.

Abstract: Techniques are disclosed relating to display devices. In some embodiments, a display device includes a display system configured to display three-dimensional content to a user. The display device is configured to discover, via a network interface, one or more compute nodes operable to facilitate rendering the three-dimensional content and receive information identifying abilities of the one or more compute nodes to facilitate the rendering. Based on the received information, the display device evaluates a set of tasks to identify one or more of the tasks to offload to the one or more compute nodes for facilitating the rendering and distributes, via the network interface, the identified one or more tasks to the one or more compute nodes for processing by the one or more compute nodes.

Abstract: A method, an apparatus and a computer program for display contents generation are provided. The disclosed solution enables display contents generation in a case where several application window surfaces are visible at the same time and the number of application window surfaces exceeds the number of available hardware layers in a display subsystem (DSS). In the disclosed solution, the display subsystem is sequentially used to composite a final display frame.

Abstract: Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.

Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

Abstract: A system and a method are disclosed for ray tracing in a pipeline of a graphic processing unit (GPU). It is determined whether a ray bounce of a first ray intersects a first primitive that is the closest primitive intersected by the ray bounce. The first ray is part of a first group of rays being processed by a first single-instruction-multiple-data (SIMD) process. The first ray is assigned by a sorting or binning unit to a second group of rays based on the intersection of the first primitive. The second group of rays is processed by a second SIMD process. The first ray is assigned to the second group of rays based on a material identification of the first primitive, an identification of the first primitive intersected by the ray bound of the first ray, a pixel location, and a bounce number of the ray bounce intersecting the first primitive.