Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

Abstract: Methods and apparatus relating to programmable power performance optimization for graphics cores are described. In one embodiment, the first frame of a scene is analyzed. It is then determined whether to optimize one or more operations, to be performed on one or more frames of the scene, based on the second frame of the scene and an idle status of one or more subsystems of a processor. And, one or more optimization operations are performed on a third frame of the scene based on the determination of whether to optimize the one or more operations. Other embodiments are also disclosed and claimed.

Abstract: A protected graphics module can send its output to a display engine securely. Secure communications with the display can provide a level of confidentiality of content generated by protected graphics modules against software and hardware attacks.

Abstract: Systems, apparatus, methods and computer program products are described below for rendering a graphical user interface by selectively compositing display contents. In general for each of one or more content producers, where each content producer is associated with content storage containing display content, display content for output is identified depending on the content consumer to which the graphical user interface is being rendered.

Abstract: One or more techniques and/or systems are provided for operating a graphics processing unit (GPU). A sensor of a computing device may collect sensor input data (e.g., camera input, touch input, video input, etc.), which may be provided to the GPU. An input process within the GPU may be invoked to process the sensor input data to generate a result that may be retained within GPU accessible memory (e.g., a touch sensor process may generate a gesture result based upon touch input from a touch panel of the computing device). An output process within the GPU may be invoked to utilize the result within the GPU accessible memory, for display rendering. In this way, latency between user input and display rendering may be mitigated by streamlining processing on the GPU by mitigating transmission of data between the GPU and a CPU of the computing device for display rendering.

Abstract: A resource used by a shader executed by a graphics processing unit is referenced using a “descriptor”. Descriptors are grouped together in memory called a descriptor heap. Applications allocate and store descriptors in descriptor heaps. Applications also create one or more descriptor tables specifying a subrange of a descriptor heap. To bind resources to a shader, descriptors are first loaded into a descriptor heap. When the resources are to be used by a set of executing shaders, descriptor tables are defined on the GPU identifying ranges within the descriptor heap. Shaders, when executing, refer to the currently defined descriptor tables to access the resources made available to them. If the shader is to be executed again with different resources, and if those resources are already in memory and specified in the descriptor heap, then the descriptor tables are changed to specify different ranges of the descriptor heap.

Abstract: Technologies related to intermediary graphics rendition are generally described. In some examples, one or more devices in a local network may be equipped to serve as real-time graphics rendering intermediary computing devices for clients in the local network. A graphics rendering manager for the local network may collect graphics processing capability information of the devices in a local network, and may select computing device(s) in the local network to serve as intermediary computing device(s). The graphics rendering manager may interact with a system controller at a server or datacenter to direct compositing flow(s) to the selected computing device(s), responsive to system controller requests to initiate intermediary graphics rendering for clients in the local network.

Abstract: A graphics processing pipeline (20) comprises first vertex shading circuitry (21) that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline. Tiling circuitry (22) then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. A second vertex shading circuitry (23) then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further.

Abstract: The application programming interface permits an application to specify resources to be used by shaders, executed by the GPU, through a data structure called the “root arguments.” A root signature is a data structure in an application that defines the layout of the root arguments used by an application. The root arguments are a data structure resulting from the application populating locations in memory according to the root signature. The root arguments can include one or more constant values or other state information, and/or one or more pointers to memory locations which can contain descriptors, and/or one or more descriptor tables. Thus, the root arguments can support multiple levels of indirection through which a GPU can identify resources that are available for shaders to access.

Abstract: An image processing method includes receiving a first image rendered by a graphics processing unit (GPU) from the GPU, comparing the first image with a second image rendered by the GPU before the first image, and controlling a rendering frequency of the GPU based on a result of comparing the first image with the second image.

Abstract: Methods and apparatus for efficiently computing vertical run length values corresponding to an image and/or identifying image patterns, e.g., bar codes and QR codes, where binary image data is stored sequentially in memory, e.g., according to a horizontal row by row basis, are described. A set of detected pixel value change location information is initialized for each column of the image and is updated as processing occurs, e.g., recording row numbers in which a pixel value change was detected between the current row and the previous row. Scanning horizontally across each row, the bitmap is processed in a horizontal fashion, the same way bitmap pixels are laid out in memory. In accordance with a feature of various embodiments of the current invention, the order of bitmap accesses is such that the spatial locality of the code is vastly improved, and the cache performance increases in comparison to a traditional approach.

Abstract: A method for the selective utilization of graphics processing unit (GPU) acceleration of database queries in database management is provided. The method includes receiving a database query in a database management system executing in memory of a host computing system. The method also includes estimating a time to complete processing of one or more operations of the database query using GPU accelerated computing in a GPU and also a time to complete processing of the operations using central processor unit (CPU) sequential computing of a CPU. Finally, the method includes routing the operations for processing using GPU accelerated computing if the estimated time to complete processing of the operations using GPU accelerated computing is less than an estimated time to complete processing of the operations using CPU sequential computing, but otherwise routing the operations for processing using CPU sequential computing.

Abstract: A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a 2-D image stored in a memory coupled to the processor. The 2-D cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a 2-D structure of the 2-D image.

Abstract: A non-blocking texture cache memory for a texture mapping pipeline and an operation method of the non-blocking texture cache memory may include: a retry buffer configured to temporarily store result data according to a hit pipeline or a miss pipeline; a retry buffer lookup unit configured to look up the retry buffer in response to a texture request transferred from a processor; a verification unit configured to verify whether result data corresponding to the texture request is stored in the retry buffer as the lookup result; and an output control unit configured to output the stored result data to the processor when the result data corresponding to the texture request is stored as the verification result.

Abstract: A method for the selective utilization of graphics processing unit (GPU) acceleration of database queries in database management is provided. The method includes receiving a database query in a database management system executing in memory of a host computing system. The method also includes estimating a time to complete processing of one or more operations of the database query using GPU accelerated computing in a GPU and also a time to complete processing of the operations using central processor unit (CPU) sequential computing of a CPU. Finally, the method includes routing the operations for processing using GPU accelerated computing if the estimated time to complete processing of the operations using GPU accelerated computing is less than an estimated time to complete processing of the operations using CPU sequential computing, but otherwise routing the operations for processing using CPU sequential computing.

Abstract: In a display device, when a receiving section receives positional information representing a position of a pointer image in a display region in a first display mode, a data generating section generates display image data corresponding to a display image based on an image corresponding to internal image data stored in an internal image memory, the above-mentioned pointer image, and the above-mentioned positional information.

Abstract: A system and method for image processing are provided. The system comprises a main computing device and a secondary computing device. The main computing device comprises a main graphics card and a main central processing unit, and the secondary computing device comprises a secondary graphics card and a secondary central processing unit. The main computing device is configured to detect the secondary computing device. The main central processing unit is configured to send a request to process raw image data together to the secondary central processing unit and allocate the raw image data to the main graphics card and the secondary graphics card after receiving a response from the secondary central processing unit. The main graphics card and the secondary graphics card are configured to process images based on the allocation of the main central processing unit.

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Abstract: A graphics processing chip includes multiple graphics pipeline cores and multi-pipeline core logic circuitry to process graphic data streams received from a processor and to drive multiple GPUs on the multiple graphics pipeline cores.

Abstract: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.