Patents Examined by Henry Tsai
-
Patent number: 12132649Abstract: A network interface controller (NIC) capable of efficient memory access is provided. The NIC can be equipped with an operation logic block, a signaling logic block, and a tracking logic block. The operation logic block can maintain an operation group associated with packets requesting an operation on a memory segment of a host device of the NIC. The signaling logic block can determine whether a packet associated with the operation group has arrived at or departed from the NIC. Furthermore, the tracking logic block can determine that a request for releasing the memory segment has been issued. The tracking logic block can then determine whether at least one packet associated with the operation group is under processing in the NIC. If no packet associated with the operation group is under processing in the NIC, tracking logic block can notify the host device that the memory segment can be released.Type: GrantFiled: August 23, 2023Date of Patent: October 29, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Igor Gorodetsky, Hess M. Hodge, Timothy J. Johnson
-
Patent number: 12130765Abstract: A process includes coupling a push-pull driver of a first bus device to a plurality of communication lines that are associated with a first bus to allow the first bus device to access the first bus using push-pull signaling. The process includes sharing a set of communication lines with the second bus. The sharing includes coupling an open drain driver of a second bus device to the set of communication lines to allow the second bus device to access the second bus using open drain signaling. The sharing includes using the set of communication lines in first time periods in which the first bus device accesses the first bus and using the set of communication lines in second time periods other than the first time periods in which the second bus device accesses the second bus. The sharing includes isolating a push-pull driver of the first bus device from the set of communication lines responsive to the second time periods.Type: GrantFiled: October 10, 2022Date of Patent: October 29, 2024Assignee: Hewlett Packard Enterprise Development LPInventor: Peter A. Hansen
-
Patent number: 12130679Abstract: A system (e.g., a power and communication system for remote components) can include a first wire, a second wire, and a first module operatively connected to the first and second wire. The first module can be configured to output power to and to communicate over the first wire and second wire. The system can include a second module operatively connected to the first module by the first wire and the second wire. The second module can be configured to receive power from the first module and to communicate with the first module over the first wire and/or second wire. The first module can be configured to modify a voltage on at least the first wire to signal to the second module to provide serial communication to the first module via the first wire and/or second wire.Type: GrantFiled: September 24, 2021Date of Patent: October 29, 2024Assignee: SIMMONDS PRECISION PRODUCTS, INC.Inventor: Robbie W. Hall
-
Patent number: 12124392Abstract: Multiple device stacks are interconnected in a ring topology. The inter-device stack communication may utilize a handshake protocol. This ring topology may include the host so that the host may initialize and load the device stacks with data and/or commands (e.g., software, algorithms, etc.). The inter-device stack interconnections may also be configured to include/remove the host and/or to implement varying numbers of separate ring topologies. By configuring the system with more than one ring topology, and assigning different problems to different rings, multiple, possibly unrelated, machine learning tasks may be performed in parallel by the device stack system.Type: GrantFiled: August 4, 2023Date of Patent: October 22, 2024Assignee: Rambus Inc.Inventor: Steven C. Woo
-
Patent number: 12124398Abstract: An input/output unit for data acquisition in a field bus system includes a microcontroller that has at least one integrated synchronous serial bus interface and a control device for direct memory access. A signal source for a digital signal is connectable to a digital data input master input, slave output (MISO) of the at least one synchronous serial bus interface. The first synchronous serial interface reads in the digital signal present at the data input MISO at a first clock rate that corresponds to a data transmission rate of the at least one synchronous serial bus interface. The control device for direct memory access forwards the read-in data words to a buffer memory, and periodically fetches the read-in data words from the buffer memory and forwards the read-in data words to a second synchronous serial bus interface or to another bus interface.Type: GrantFiled: September 29, 2020Date of Patent: October 22, 2024Assignee: PHOENIX CONTACT GMBH & CO. KGInventor: Klaus Wessling
-
Patent number: 12124403Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing system may include: a processor system including at least one first processor core having a first instruction set architecture (ISA); a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA; and control logic to suspend execution of the program by the at least one first processor core and cause at least one second processor core to resume execution of the program, wherein the at least one second processor core has a second ISA different from the first ISA; wherein the program is to generate data having an in-memory representation compatible with both the first ISA and the second ISA.Type: GrantFiled: March 14, 2022Date of Patent: October 22, 2024Assignee: Intel CorporationInventors: Eliezer Tamir, Ben-Zion Friedman
-
Patent number: 12124400Abstract: A data communication apparatus coupled to a serial bus has a protocol controller that configures a first plurality of subordinate devices with device identifiers unique within the first plurality of subordinate devices and configures a second plurality of subordinate devices with device identifiers unique within the second plurality of subordinate devices. A sequence start condition transmitted over the serial bus indicates either a first communication mode in which a clock signal is provided to the serial bus or a second communication mode in which no clock signal is provided. A device identifier associated with the first plurality of subordinate devices is used to transmit a first datagram over the serial bus in the first communication mode, and a device identifier associated with the second plurality of subordinate devices is used to transmit a second datagram over the serial bus in the second communication mode.Type: GrantFiled: January 19, 2023Date of Patent: October 22, 2024Assignee: QUALCOMM IncorporatedInventors: Umesh Srikantiah, Lalan Jee Mishra, Francesco Gatta, Richard Dominic Wietfeldt
-
Patent number: 12124709Abstract: The present application discloses a computing system and an associated method. The computing system includes a first host, a second host, a first memory extension device and a second memory extension device. The first host includes a first memory, and the second host includes a second memory. The first host has a plurality of first memory addresses corresponding to a plurality of memory spaces of the first memory, and a plurality of second memory addresses corresponding to a plurality of memory spaces of the second memory. The first memory extension device is coupled to the first host. The second memory extension device is coupled to the second host and the first memory extension device. The first host accesses the plurality of memory spaces of the second memory through the first memory extension device and the second memory extension device.Type: GrantFiled: December 12, 2022Date of Patent: October 22, 2024Assignee: ALIBABA (CHINA) CO., LTD.Inventors: Tianchan Guan, Yijin Guan, Dimin Niu, Hongzhong Zheng
-
Patent number: 12124399Abstract: A USB controller includes: a USB interface that receives an isochronous timestamp packet (ITP) from a host device that includes a current time value from the host device and a delay value associated with each hub through which the ITP passed; controller hardware that initiates a counter, sends a link delay measurement (LDM) link management packet (LMP) request to a nearest upstream hub, stores a first timestamp that corresponds to when the LDM LMP request was sent, receives an LDM LMP response from the nearest upstream hub, and stores a second timestamp that corresponds to when the LDM LMP response was received; and controller software that calculates a link delay between the USB controller and the nearest upstream hub based on the first and second timestamps and delay information included in the LDM LMP response, and adjusts the counter value based on the calculated link delay.Type: GrantFiled: January 5, 2023Date of Patent: October 22, 2024Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Karthik Sivaramakrishnan, Hamid Khodabandehlou, Godwin Arulappan, Jagadeesan Rajamanickam, Manaskant Dipakkumar Desai, Nimish Thakkar
-
Patent number: 12124397Abstract: The present technology may include a first latch circuit configured to store, as first data, data that is transmitted through a first signal line, a second latch circuit configured to store, as a plurality of second data, the data that is transmitted through the first signal line by sorting the data by a plurality of second signal lines that are connected to the first signal line in common, and a data bus inversion engine configured to selectively perform a first mode in which the data bus inversion engine generates a data bus inversion flag by comparing the first data with current input data and a second mode in which the data bus inversion engine generates the data bus inversion flag by comparing the plurality of second data with the current input data.Type: GrantFiled: February 24, 2023Date of Patent: October 22, 2024Assignee: SK hynix Inc.Inventors: Hong Ki Moon, Seok Bo Shim
-
Patent number: 12126513Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, an external memory interface configured to couple the on-chip memory with an external memory providing a backing store to the on-chip memory, and bandwidth monitor configured to measure a bandwidth utilization of the external memory. The network processor also includes a processor configured to apply the bandwidth utilization of the external memory to a congestion notification profile, to generate one or more congestion notifications based on the bandwidth utilization applied to the congestion notification profile, and to send the one or more congestion notifications to the source device to request decreasing packet rate for decreasing the bandwidth utilization of the external memory.Type: GrantFiled: December 10, 2021Date of Patent: October 22, 2024Assignee: Nokia Solutions and Networks OyInventors: Brian Alleyne, Matias Cavuoti, Li-Chuan Egan, Mimi Dannhardt, Krishnan Subramani, Mohamed Abdul Malick Mohamed Usman, Roxanna Ganji, Stephen Russell
-
Patent number: 12117955Abstract: This application provides a spread spectrum clock negotiation method, and a peripheral component interconnect express device and system, to implement dynamic negotiation between a transmit end and a receive end on an SSC capability in the peripheral component interconnect express system. The method includes: A second PCIe device generates first indication information, where the first indication information is used to indicate whether the second PCIe device has a spread spectrum clock capability. The second PCIe device sends the first indication information to a first PCIe device. The first PCIe device determines, based on the first indication information, whether to perform spread spectrum clock on a reference clock of the first PCIe device.Type: GrantFiled: September 23, 2022Date of Patent: October 15, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Er Nie, Kun Wang, Pan Li
-
Patent number: 12117950Abstract: A method of providing data communication between a first device and a second device includes, establishing a first communication link with a downstream device connected to the second device using a first mode via a USB-type interface, wherein in the first mode the USB-type interface utilizes a first set of USB communication lanes; establishing a second communication link with the first device via the USB-C port using an Alternate mode wherein the Alt-mode utilizes the first set of USB communication lanes; and, in accordance with establishing the second communication link, changing a mode of the first communication link so that the first communication link does not communicate via the first set of USB communication lanes.Type: GrantFiled: June 4, 2021Date of Patent: October 15, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Julia Jacinta Busono, Robert Glenn Rundell
-
Patent number: 12117952Abstract: The multi-path server comprises four circuits. Each circuit comprises a PCH, an extended module, a switch module, and a CPU. An extended module in the first circuit is connected to a switch module in the second circuit, a switch module in the third circuit, and a switch module in the fourth circuit. An extended module in the third circuit is connected to a switch module in the fourth circuit. A switch module performs switching action according to a target partition instruction, and a PCH performs in-place action according to the target partition instruction, such that each said circuit forms a target partition, and PMSYNC signals are interconnected in the target partition. A multi-path server signal interconnection system is also provided.Type: GrantFiled: September 28, 2021Date of Patent: October 15, 2024Assignee: Shandong Yingxin Computer Technologies Co., Ltd.Inventor: Xiangtao Kong
-
Patent number: 12117958Abstract: The present invention is related to a computing device (CD), in particular for automotive applications, with a safe and secure coupling between virtual machines (VMi) and a peripheral component interconnect express device (PCIe-D). The invention is further related to a vehicle comprising such a computing device (CD). The computing device (CD) comprises one or more virtual machines (VMi) and a virtual switch (VS). The virtual switch (VS) is configured to provide a safe and secure coupling between the one or more virtual machines (VMi) and at least one peripheral component interconnect express device (PCIe-D) configured to support single-root input/output virtualization, to which the computing device (CD) is connected.Type: GrantFiled: May 13, 2021Date of Patent: October 15, 2024Assignee: Elektrobit Automotive GmbHInventors: Helmut Gepp, Bekim Chilku, Georg Gaderer, Michael Ziehensack
-
Patent number: 12117953Abstract: A server rack has server sleds, each including a motherboard upon which is mounted: a memory module, a cache, at least one CPU connected to the cache, a memory controller connected to the cache and the memory module, an I/O hub, and a fabric interface (FIC) having a memory bridge and optical transceivers, where this memory bridge is connected to the I/O hub through this motherboard. The rack also has a memory sled disaggregated from the server sleds and that includes: a motherboard upon which is mounted: memory modules and a FIC having a memory bridge, a memory controller and optical transceivers, wherein this memory controller is connected to these memory modules through this motherboard, and wherein this memory bridge connects the memory controller to the optical transceivers. The rack has a photonic cross-connect switch interconnected by optical fiber cables to the optical transceivers of the server and memory sleds.Type: GrantFiled: January 24, 2024Date of Patent: October 15, 2024Assignee: Drut Technologies Inc.Inventors: Jitender Miglani, Dileep Desai
-
Patent number: 12117948Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.Type: GrantFiled: October 31, 2022Date of Patent: October 15, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Liran Liss, Rabia Loulou, Idan Burstein, Tzuriel Katoa
-
Patent number: 12117327Abstract: An M-BUS receiving circuit (8) and an M-BUS-based 4G water meter collector. The M-BUS receiving circuit (8) is disposed between a control unit (2) and an M-BUS overcurrent protection circuit, and is used for connecting the control unit (2) and the M-BUS overcurrent protection circuit. The M-BUS receiving circuit (8) consists of a voltage-stabilizing chip U1, Schmitt triggers U5B and U5C, voltage comparators U3A and U3B, triodes Q2 and Q4, diodes D1, D2, D8-D11, operational amplifiers U15A and U15B, voltage-stabilizing diodes ZW10 and ZW11, and several resistance-capacitance circuits. The M-BUS receiving circuit (8) can greatly increase the signal-to-noise ratio, and the reliability and stability thereof are significantly improved. Similarly, the M-BUS-based 4G water meter collector can effectively improve the stability of water meter data collection.Type: GrantFiled: January 29, 2022Date of Patent: October 15, 2024Assignee: SHENZHEN CHUANGREN TECHNOLOGY CO., LTD.Inventors: Dong Li, Jubao Nie, Guanru Li, Guanxi Li, Junsheng Zhu
-
Patent number: 12118133Abstract: A handshake circuit portion for performing a handshake procedure to facilitate data reception by an associated circuit portion is provided. The handshake circuit portion comprises a request signal input for detecting a request signal from a further handshake circuit portion associated with a further circuit portion, an acknowledge signal output for asserting an acknowledge signal for the further handshake circuit portion, and a blocking signal input for detecting a blocking signal from the associated circuit portion. The handshake circuit portion is arranged to detect a request signal via the request signal input, determine if a blocking signal is present on the blocking signal input, and if a blocking signal is not present on the blocking signal input, respond to the request signal by asserting an acknowledge signal via the acknowledge signal output.Type: GrantFiled: April 11, 2022Date of Patent: October 15, 2024Assignee: Nordic Semiconductor ASAInventors: Arne Wanvik VenĂ¥s, Karianne Krokan Kragseth, Per-Carsten Skoglund, Steffen Eidal Wiken, Vegard Endresen
-
Patent number: 12117959Abstract: A communication apparatus includes an I2C logic circuit, an I3C logic circuit, an external terminal, and a switch circuit. The I2C logic circuit controls communication via a control data bus in accordance with an I2C (Inter?Integrated Circuit) communication standard. The I3C logic circuit controls the communication via the control data bus in accordance with an I3C (Improved Inter Integrated Circuit) communication standard. The external terminal is coupled to the control data bus. The switch circuit controls coupling between one of the I2C logic circuit and the I3C logic circuit, and the external terminal.Type: GrantFiled: December 4, 2020Date of Patent: October 15, 2024Assignee: Sony Semiconductor Solutions CorporationInventor: Yuichi Mizutani