Abstract: A data processing apparatus and a program data setting method that can minimize a manufacturing cost. The data processing apparatus includes a plurality of In System Programming (ISP) devices to store program data used to drive the data processing apparatus, a connector to receive the program data from an external program providing device, and a switch to switch a connection between the connector and the plurality of ISP devices. The data processing apparatus can adjust the connection between the connector and the plurality of ISP devices using the switch. Accordingly, the data processing apparatus does not require an additional connector or a separate program to distribute the program data received at the connector to each ISP device so that the manufacturing cost can be minimized and a structure can be simplified.

Abstract: Described is a distributed copying technique that may be used in migrating large amounts of data from one or more source devices to one or more destination devices. The data source is divided into partitions. As Fibre Channel adapters (FAs) become available, each of the FAs may copy a partition of the data. In connection with specifying paths used for the distributed copying technique, a preferred path selection (source port-target port mapping) may be made by executing code in a controlling data storage system to perform discovery processing. The preferred path selection is used for the duration of the distributed copying unless the preferred path is unable to transmit data. A target port of the preferred path may be randomly selected from all accessible target ports, and/or in accordance with a specified portion of the target ports. Preferred paths may also be specified using an API (application programming interface).

Abstract: In a computer system employing PCI Express (PCIe) links, the PCIe bandwidth is increased by configuring an endpoint device with at least two PCIe interfaces, and coupling the first of these interfaces with a PCIe interface of a system controller and the second of these PCIe interfaces with an expansion PCIe interface of an I/O controller. Therefore, the endpoint device's performance becomes more efficient. For example, if the endpoint device is a graphics processing unit, then the endpoint device can execute more frames per second. When a read request is split up and issued as multiple read requests over the at least two PCIe interfaces, the multiple read completion packets that are received in response thereto are ordered in accordance with the timing of the multiple read requests.

Abstract: A method and apparatus for enabling enhanced interaction across a USB interconnect between a host and a peripheral device capable of performing a plurality of functions including enabling selection and execution of a vendor-specific support software supporting peripheral devices of a specific vendor by sending a first identification data to the host indicating that the peripheral device is of the same specific vendor and indicating that the peripheral device performs at least one of the functions indicated to be supported by the vendor-specific support software, awaiting receipt of an indication from the host that the vendor-specific support software has been selected and executed, simulating a detachment from and attachment to the host; and enabling the vendor-specific support software to again be selected and executed by sending a second identification data to the host indicating that the peripheral device is of the same specific vendor and indicating that the peripheral device performs multiple ones of the

Abstract: A data transfer request of a data pro cessing device with respect to a synchronous memory is divided by a burst transfer length unit request dividing section into a plurality of data transfer requests in which a data transfer amount is an amount of data to be burst-transferred at a time and the data to be burst-transferred at a time is within a single memory bank. An assembling section assembles the divided data transfer requests into a plurality of new data transfer requests obtained by combining the divided data transfer requests, one for each memory bank. A data processing device can efficiently access continuous data stored in a plurality of memory banks, and is useful as a memory access control circuit of controlling an access operation of a data processing device with respect to a synchronous memory.

Abstract: An extended Universal-Serial Bus (EUSB) host has reduced loading by using radio frequency (RF) transceivers or direct wiring traces rather than a pair of legacy USB cables. The reduced loading opens the eye pattern. The EUSB device transfers internal data using chained Direct-Memory Access (DMA). Registers in a DMA controller point to a vector table that has vector entries, each pointing to a destination and a source. The source is a memory table for a memory group. The memory table has entries for several memory segments. Each memory-table entry has a pointer to a memory segment and a byte count for the segment. Once all bytes in the segment are transferred, a flag in the entry indicates when another memory segment follows within the memory group. When an END flag is read, then vector table is advanced to the next vector entry, and another memory group of memory segments processed.

Abstract: A forced lock-step operation between a CPU (software) and the hardware is eliminated by unburdening the CPU from monitoring the hardware until it is finished with its task. This is done by providing a data/control message queue into which the CPU writes combined data/control messages and places an End tag into the queue when finished. The hardware checks the content of the message queue and starts decoding the incoming data. The hardware processes the data read from the message queue and the processed data is then written back into the message queue for use by the software. The hardware raises an interrupt signal to the CPU when reaching the End tag. Speed differences between hardware and software can be compensated for by changing the depth of the queue.

Abstract: A universal serial bus (USB) with single port and a host controller thereof are provided. The USB comprises a USB port, a speed detection circuitry, a start of frame (SOF) generator, and a host controller. The USB port is electrically coupled to an external circuitry. The speed detection circuitry is electrically coupled to the USB port for detecting a transmission speed between the USB and the external circuitry via the USB port to provide a detecting result. The SOF generator is electrically coupled to the speed detection circuitry for receiving the detecting result and outputting a SOF signal, to determine a cycle of the SOF signal based on the detecting result. The host controller is electrically coupled to the SOF generator and the speed detection circuitry for adjusting the host controller based on SOF signal cycle to comply with the USB 2.0, USB 1.1 and USB 1.0 transmission standards.

Abstract: Upon reception of data via a first communication device, a unit connects the first communication device with a storage unit to store the data to be transferred and, after completion of data reception, the unit switches connections of the storage unit to a second communication device and transmits the stored data to the second communication device.

Abstract: A system for tagged interrupt forwarding comprises a multiprocessor including a first and a second processor, an I/O device, and I/O management software. In response to an application I/O request, the I/O management software may be configured to prepare a request descriptor at the first processor, including an identification of the first processor. The I/O management software may then send a hardware or device-level I/O request to the I/O device. When the I/O device completes the requested hardware I/O operation, it may send a response, which may be received at the second processor. I/O management software at the second processor may be configured to transfer control for processing the response back to the first processor at which the I/O request was initiated, using the tag to identify the first processor. Processing of the response may then be completed at the first processor.

Abstract: Some embodiments of the invention include apparatus, systems, and methods to perform universal serial bus (USB) suspend and resume operations based on active communication between USB devices to improve power management. Other embodiments are described and claimed.

Abstract: The invention relates to a semi-conductor component, in particular a semi-conductor component configured to be connected with a bus, in particular a LIN bus system, as well as a process for operating a system module, configured to be connected with a bus, in particular a LIN bus system, which includes emitting a data record and allocated check bits while operating the system module in a first operating mode, such that to operate the system module in a second operating mode, check bits differently generated in comparison with the first operating mode are used.

Abstract: The present invention relates to reduction of power consumption of electronic mass storage devices, and more particularly to such a reduction of power consumption in mobile infotainment products. These devices are equipped with a subsystem comprising a mass storage device (48) and a buffer memory (43, 44). The size of the buffer memory (43, 44) is adapted in such a way that optimally low power consumption is achieved. This accomplishment by activating or deactivating memory banks (45) comprised in the buffer memory chips. The amount of memory banks (45) activated is determined by operating characteristics of the subsystem, e.g. a desired bit-rate to be achieved for transmissions to/from the mass storage device (48).

Abstract: In one embodiment, a system comprises at least one processor and a peripheral interface controller coupled to the processor. Further coupled to receive transactions from a peripheral interface, the peripheral interface controller is configured to accumulate freed credits for a given transaction type of a plurality of transaction types that are not yet returned to a transmitter on the peripheral interface. The peripheral interface controller is also configured to cause transmission of a flow control update transaction on the peripheral interface responsive to a number of the freed credits exceeding a threshold amount that is less than a total number of credits allocated to the given transaction type.

Abstract: Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.

Abstract: An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated.

Abstract: A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO unit is provided. In the virtual FIFO DMA device, a DMA unit is for transferring data between the UART unit and the virtual FIFO unit. A virtual FIFO controller, which has a read pointer and a write pointer, is electrically connected with the DMA unit. When the DMA unit reads data from or writes data into the virtual FIFO unit, the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer. A virtual port is electrically connected to the DMA unit and the processor. A processor reads data from or writes data into the virtual FIFO unit via the virtual port and the DMA unit.

Abstract: A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.

Abstract: A serial transmission controller, a serial transmission decoder and a serial transmission method thereof are disclosed. First, a current address and an access address are compared to select one of a plurality of transmission address modes as an access address mode and then to produce corresponding address information. The transmission address modes use different bits to transmit the address information respectively. According to the access address mode, an access command is selected from a serial command set. Finally, the access command and the address information are transmitted to a serial interface serially. After the access command is encoded to different length of bits, the encoded access command is transmitted to the serial interface so as to reduce the transmission bits and improve the transmission efficiency.

Abstract: A method and apparatus is provided wherein a central Credit Controller Entity (CCE) is connected to a PCIE fabric environment by means of several buses. Flow Control information sent to the CCE over two of the buses indicates the buffer storage capacity that is available at respective Receiver components in the PCIE fabric. The CCE processes the Flow Control information, to generate updates that are sent by a third bus to Transmitter components corresponding to the Receivers. In one useful embodiment, directed to a method of Flow Control management, the CCE provides a repository adapted to store credit count information that represents the available storage capacity of respective Receivers. The method further comprises routing further credit count information from a given Receiver to the CCE, for storage in the repository, following each of successive events that affect the storage capacity of the given Receiver.