Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

Abstract: There is provided a technique including: (a) forming a thin film containing a predetermined element, oxygen and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a source gas containing the predetermined element, carbon and a halogen element having a chemical bond between the predetermined element and carbon to the substrate; (a-2) supplying an oxidizing gas to the substrate; and (a-3) supplying a catalytic gas to the substrate; (b) removing a first impurity from the thin film by thermally processing the thin film at a first temperature higher than a temperature of the substrate in (a); and (c) removing a second impurity different from the first impurity from the thin film by thermally processing the thin film at a second temperature equal to or higher than the first temperature after performing (b).

Abstract: The present invention provides a method for controlling a critical dimension of shallow trench isolations in a STI etch process, comprises the following steps: before the STI etch process, pre-establishing a mapping relation between a post-etch and pre-etch critical dimension difference of a BARC layer and a thickness of the BARC layer; and during the STI etch process after coating the BARC layer, measuring the thickness of the BARC layer and determining a trimming time for a hard mask layer according to a critical dimension difference corresponding to the measured thickness in the mapping relation and a critical dimension of a photoresist pattern, then performing a trimming process for the hard mask layer lasting the trimming time to make a critical dimension of the hard mask layer equal to a required critical dimension of an active area, and etching a substrate to form shallow trenches with a predetermined critical dimension.

Abstract: A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die.

Abstract: The present disclosure discloses a mask that comprises a nonmetallic layer and a hollow-out pattern through the nonmetallic layer. The present disclosure further discloses a method of manufacturing the mask, which comprises manufacturing the hollow-out pattern through the nonmetallic layer.

Abstract: A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

Abstract: A method for fabricating a semiconductor structure and a solid precursor delivery system for a semiconductor fabrication is provided, the method including: providing a solid precursor having a first average particle size; solving the solid precursor in an organic solvent into an intermediate; recrystallizing the intermediate to form solid granules, wherein the solid granules has a second average particle size larger than the first average particle size; vaporizing the solid granules to form a film-forming gas; and depositing the film-forming gas on a substrate to form a resistance film.

Abstract: A liquid crystal display device with an increased pixel aperture ratio is provided. A liquid crystal display device that displays an image with high contrast and high luminance is provided. The liquid crystal display device includes a first pixel electrode; a second pixel electrode; a transistor; a capacitor; a first insulating film; a second insulating film; and a third insulating film. The transistor includes a gate electrode; a gate insulating film; a first oxide semiconductor film; and a source electrode and a drain electrode. One of a pair of electrodes of the capacitor includes a second oxide semiconductor film. The first insulating film is provided over the first oxide semiconductor film. The second insulating film is provided over the second oxide semiconductor film such that the second oxide semiconductor film is sandwiched between the first insulating film and the second insulating film. The third insulating film overlaps with an end of the first pixel electrode.

Abstract: A semiconductor wafer is provided. The semiconductor wafer includes a base layer having an active region and an edge region. A number of semiconductor devices is formed on the active region. The semiconductor wafer also includes a wafer identification. The wafer identification is formed on the edge region and used for identifying the semiconductor wafer. The semiconductor wafer further includes an alignment mark. The alignment mark is formed on the edge region and is used for performing an alignment process of the semiconductor wafer.

Abstract: A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a top portion of a silicon cap layer located in direct contact with a first diamond shaped epitaxial layer surrounding a first fin and a second diamond shaped epitaxial layer surrounding a second fin. The metal layer extends from the top portion of the silicon cap layer in direct contact with the first diamond shaped epitaxial layer to the top portion of the silicon cap layer in direct contact with the second diamond shaped epitaxial layer. The conducted laser-based anneal treatment forms a silicide layer, a portion of the silicide layer between the first and the second diamond shaped epitaxial layers is substantially thicker than a portion of the silicide layer in contact with the first and the second diamond shaped epitaxial layers.

Abstract: A method of making a graphene base transistor with reduced collector area comprising forming a graphene material layer, forming a collector material, depositing a dielectric, planarizing the dielectric, cleaning and removing the native oxide, transferring a base graphene material layer to the top surface of the graphene material layer, bonding the base graphene material layer, and photostepping and defining a second graphene material layer. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region. A graphene base transistor with reduced collector area comprising an electron emitter region, an electron collection region, and a base region.

Abstract: A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

Abstract: There is provided a semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes.

Abstract: An image sensor can include a photoelectric conversion part of an active region of a substrate and a trench in the substrate. A transfer transistor gate electrode can extend from outside the trench into the trench and terminate in the trench to provide an exposed portion of the trench in the photoelectric conversion part.

Abstract: A semiconductor device includes first and second second-conductivity-type region groups containing multiple second-conductivity-type regions that are disposed on a first silicon carbide semiconductor layer of a first conductivity type, arrayed in parallel following one direction with a space between each other, and first and second electrodes disposed on the first silicon carbide semiconductor layer and forming a Schottky junction with the first silicon carbide semiconductor layer. The first electrode covers a position where a distance from adjacent first and second second-conductivity-type regions included in a first second-conductivity-type region group, and a distance from a third second-conductivity-type region included in a second second-conductivity-type region group and adjacent to the first and second second-conductivity-type regions, are equal.

Abstract: An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other.

Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region.

Abstract: A change in electrical characteristics is inhibited and reliability is improved in a semiconductor device using a transistor including an oxide semiconductor. One embodiment of a semiconductor device including a transistor includes a gate electrode, first and second insulating films over the gate electrode, an oxide semiconductor film over the second insulating film, and source and drain electrodes electrically connected to the oxide semiconductor film. A third insulating film is provided over the transistor and a fourth insulating film is provided over the third insulating film. The third insulating film includes oxygen. The fourth insulating film includes nitrogen. The amount of oxygen released from the third insulating film is 1×1019/cm3 or more by thermal desorption spectroscopy, which is estimated as oxygen molecules. The amount of oxygen molecules released from the fourth insulating film is less than 1×1019/cm3.

Abstract: Disclosed are a light emitting device. The light emitting device include first and second lead frames, a first body on the first and second lead frames and including an open region, a second body on the first body and including a first opening, a light emitting chip on the opening region, and a transmissive layer on the light emitting chip. The first body and the second body are formed of a resin material. A top surface of the first body is located at a position lower than a position of a top surface of the light emitting chip. The second body includes a bottom surface located at a position lower than the position of the top surface of the light emitting chip. The first body comprises an inclined part around the light emitting chip. The first body includes a reflectance material and the second body includes a transmissive material.