Patents Examined by Herve-Louis Y Assouman
  • Patent number: 11574965
    Abstract: The present disclosure provides a photodiode, a display substrate, and manufacturing methods thereof, and a display device. The method for manufacturing the photodiode includes: forming a semiconductor material layer on a base substrate in a non-display region of a display substrate, the semiconductor material layer including a first contact area, a second contact area, and a semiconductor area sandwiched therebetween; processing the first contact area of the semiconductor material layer to form a first contact electrode; processing portions of the semiconductor material layer and the second contact area away from the base substrate in the semiconductor area, to form a first semiconductor layer and a second semiconductor layer stacked, the second semiconductor layer being located on a side of the first semiconductor layer away from the base substrate; and processing the second semiconductor layer in the second contact area to form a second contact electrode.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: February 7, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Mei Li
  • Patent number: 11569170
    Abstract: A semiconductor device is provided, the semiconductor device comprising a substrate having merged cavities in the substrate. An active region is over the merged cavities in the substrate. A thermally conductive layer is in the merged cavities in the substrate, whereby the thermally conductive layer at least partially fills up the merged cavities in the substrate. A first contact pillar connects the thermally conductive layer in the merged cavities in the substrate with a metallization layer above the active region.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: January 31, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Siva P. Adusumilli, Mark David Levy, Ramsey Hazbun, Alvin Joseph, Steven Bentley
  • Patent number: 11563131
    Abstract: In an illuminance sensor, a slow axis of a first quarter-wave plate has a relation of +45° or ?45° in regard to a polarization direction of a first linear polarization plate; a relation of a slow axis of a first portion of a second quarter-wave plate in regard to a polarization direction of a second linear polarization plate is the same with relation of the slow axis of the first quarter-wave plate in regard to the polarization direction of the first linear polarization plate, that is, +45° or ?45°; and a relation of a slow axis of a second portion of the second quarter plate in regard to the polarization direction of the second linear polarization plate is ?45° or +45° that is opposite in sign to the relation of the slow axis of the first quarter-plate in regard to the polarization direction of the first linear polarization plate.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: January 24, 2023
    Assignee: ROHM Co., Ltd.
    Inventor: Yoshitsugu Uedaira
  • Patent number: 11557725
    Abstract: According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: January 17, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Yoshinori Kumura
  • Patent number: 11557550
    Abstract: An electronic chip includes at least an electronic circuit disposed on a front face of a substrate; and an embrittlement structure comprising at least blind holes, each extending through a rear face of the substrate and a portion of the thickness of the substrate and each having a section, in a plane parallel to the rear face of the substrate, of surface area S and having a closed outer contour, the shape of which includes at least one radius of curvature R, such that S>?·R2.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: January 17, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stephan Borel, Lucas Duperrex
  • Patent number: 11538948
    Abstract: The present disclosure is directed to photovoltaic junctions and methods for producing the same. Embodiments of the disclosure may be incorporated in various devices for applications such as solar cells and light detectors and may demonstrate advantages compared to standard materials used for photovoltaic junctions such as silica. An example embodiment of the disclosure includes a photovoltaic junction, the junction including a light absorbing material, an electron acceptor for shuttling electrons, and a metallic contact. In general, embodiments of the disclosure as disclosed herein include photovoltaic junctions which provide absorption across one or more wavelengths in the range from about 200 nm to about 1000 nm, or from near IR (NIR) to ultra-violet (UV). Generally, these embodiments include a multi-layered light absorbing material that can be formed from quantum dots that are successively deposited on the surface of an electron acceptor (e.g., a semiconductor).
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: December 27, 2022
    Assignee: University of South Carolina
    Inventors: Mathew Kelley, Andrew B. Greytak, Mvs Chandrashekhar, Joshua Letton
  • Patent number: 11532704
    Abstract: A semiconductor device has a cell part and a terminal part set in the device. The terminal part encloses the cell part. The semiconductor device includes a first electrode, a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type, and an insulating layer. The first semiconductor layer is formed above the first electrode. The second semiconductor layer is provided in an upper portion of the first semiconductor layer, and has an impurity concentration profile along a vertical direction including a plurality of peaks. The insulating layer is provided on the second semiconductor layer.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: December 20, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Keiko Kawamura, Tomoko Matsudai, Yoko Iwakaji, Kaori Fuse
  • Patent number: 11532640
    Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Jong Chia, Chung-Te Lin, Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang
  • Patent number: 11532751
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Shih-Wei Peng, Wei-Cheng Lin, Lei-Chun Chou
  • Patent number: 11515173
    Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Chen, Yu-Min Liang, Yen-Ping Wang, Jiun Yi Wu, Chen-Hua Yu, Kai-Chiang Wu
  • Patent number: 11515207
    Abstract: Methods of producing a self-aligned structure comprising a metal chalcogenide are described. Some methods comprise forming a metal-containing film in a substrate feature and exposing the metal-containing film to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise forming a metal-containing film in a substrate feature, expanding the metal-containing film to form a pillar and exposing the pillar to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise directly forming a metal chalcogenide pillar in a substrate feature to form a self-aligned structure comprising a metal chalcogenide. Methods of forming self-aligned vias are also described.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: November 29, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Amrita B. Mullick, Srinivas Gandikota
  • Patent number: 11508774
    Abstract: An image sensor device is disclosed, which blocks noise of a pad region. The image sensor device includes a substrate including a first surface and a second surface that are arranged to face each other, a pad disposed over the first surface of the substrate, and a through silicon via (TSV) formed to penetrate the substrate, and disposed at both sides of the pad in a first direction.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 22, 2022
    Assignee: SK hynix Inc.
    Inventor: Sung Ryong Lee
  • Patent number: 11508925
    Abstract: A photovoltaic device (10) comprising a photoactive body between two electrodes (contact 1, contact 2). The body comprises semiconductor particles (24) embedded in a semiconductor matrix (22). The particles and matrix are electronically or optically coupled so that charge carriers generated in the particles are transferred directly or indirectly to the matrix. The matrix transports positive charge carriers to one of the electrodes and negative charge carriers to the other electrode. The particles are configured so that they do not form a charge carrier transport network to either of the electrodes and so perform the function of charge carrier generation but not charge carrier transport.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: November 22, 2022
    Assignee: UNIVERSITY OF ULSTER
    Inventor: Davide Mariotti
  • Patent number: 11502036
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed within the semiconductor layer. The first insulating film is formed on the inner side surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected with the semiconductor substrate and formed on the inner side surface of the first trench through the first insulating film. In plan view, a first length of the first trench in an extending direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extending direction, and equal to or less than 30 ?m.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: November 15, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirokazu Sayama, Fumihiko Hayashi, Junjiro Sakai
  • Patent number: 11502024
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first semiconductor element, a first redistribution layer, a second redistribution layer, and a conductive via. The first semiconductor element has a first active surface and a first back surface opposite to the first active surface. The first redistribution layer is disposed adjacent to the first back surface of the first semiconductor element. The second redistribution layer is disposed adjacent to the first active surface of the first semiconductor element. The conductive via is disposed between the first redistribution layer and the second redistribution layer, where the conductive via inclines inwardly from the second redistribution layer to the first redistribution layer.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: November 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Patent number: 11495687
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kuo-Cheng Chiang, Ru-Gun Liu, Wei-Hao Wu, Yi-Hsiung Lin, Chia-Hao Chang, Lei-Chun Chou
  • Patent number: 11495508
    Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: November 8, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Simone Rascuna′, Claudio Chibbaro, Alfio Guarnera, Mario Giuseppe Saggio, Francesco Lizio
  • Patent number: 11489025
    Abstract: A display device including a base layer, a circuit layer, a light emitting device layer, an organic layer, and a touch sensing unit. The base layer includes a display area and a non-display area. A plurality of insulation patterns overlaps the non-display area. The organic layer is disposed on the light emitting device and overlaps the plurality of insulation patterns and the organic light emitting diode. At least a portion of the plurality of touch signal lines overlaps the plurality of insulation patterns.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: November 1, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Se-ho Kim, Wonkyu Kwak, Ji-eun Lee, Yohan Kim, Dong-seop Park, Kwangsik Lee, Jaesun Lee, Sungho Cho
  • Patent number: 11489012
    Abstract: A method of producing a recurrent neural network computer includes consecutive steps of providing a substrate with a first electrode; structuring the first electrode by etching using a first mask made of block copolymers, such that said electrode has free regions which are randomly spatially distributed; forming a resistive-RAM-type memory layer on the first structured electrode; forming a second electrode on the memory layer; and structuring the second electrode by etching, using a second mask made of block copolymers such that said electrode has free regions which are randomly spatially distributed.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: November 1, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Elisa Vianello, Catherine Carabasse, Selina La Barbera, Raluca Tiron
  • Patent number: 11488893
    Abstract: Provided is a semiconductor device having high planarity in an in-plane direction. This semiconductor device includes a semiconductor substrate, a first plating film pattern, a second plating film pattern, and an insulating layer. The semiconductor substrate has a first surface, and a second surface on a side opposite to the first surface. The first plating film pattern includes a first portion that covers a first regional portion of the first surface, and a second portion that is stacked to cover a portion of the first portion. The second plating film pattern includes a third portion that covers a second regional portion different from the first regional portion of the first surface, and also includes a fourth portion that is stacked to cover a portion of the third portion. A portion between the second portion and the fourth portion is filled with the insulating layer.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: November 1, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takahiro Kamei, Yoichi Ootsuka