Abstract: A photoelectric conversion device includes: a substrate; a photodetection film including a first surface facing the substrate and a second surface opposing the first surface; first electrodes provided between the substrate and the photodetection film; a second electrode provided between the substrate and the photodetection film and including a first portion overlapped with the first surface and a second portion not overlapped therewith when viewed from a normal direction of the substrate; a third electrode provided on the second surface of the photodetection film and including a third surface facing the second surface; wiring allowing for conduction between the second and third electrodes; and a first conductive plug connected with the first portion and extending toward the substrate. Material of the first conductive plug differs from that of the second electrode. The wiring is in contact with a side surface of the photodetection film and the second portion.

Abstract: A display device includes a display panel including a first pixel area and a second pixel area. The first pixel area includes a first pixel, a second pixel, and a third pixel, and the second pixel area includes a fourth pixel, a fifth pixel, and a sixth pixel. The first pixel and the second pixel are arranged to be adjacent to each other in a first direction, and the third pixel is arranged to be adjacent to the first pixel and the second pixel in a second direction that intersects the first direction. The third pixel and the fourth pixel emitting a same color are arranged to be adjacent to each other in the second direction, the fifth pixel is spaced apart from the first pixel in the second direction, and the sixth pixel is spaced apart from the second pixel in the second direction.

Abstract: An array substrate and a display panel are disclosed. The display panel includes the array substrate. An ion injection stopper layer and an active layer of the array substrate correspond to at least part of the channel part. The ion injection stopper layer blocks ions from being injected into the channel part. Therefore, an effective channel length of oxide TFTs is reduced. A width of a channel of the oxide TFTs can be reduced without changing a width-length ratio of the oxide TFTs. As such, a size of the oxide TFTs can be reduced, and an aperture ratio of the display panel is increased.

Abstract: A method includes forming a semiconductor fin; forming a gate dielectric layer over the semiconductor fin; depositing a first work function metal layer over the gate dielectric layer, the first work function metal layer having a first concentration of a work function material; depositing a second work function metal layer over the first work function metal layer, the second work function metal layer having a second concentration of the work function material, wherein the first concentration is higher than the second concentration; and forming a gate electrode over the second work function metal layer.

Abstract: A semiconductor device includes first and second power supply lines formed in a first wiring layer and extending in a first direction; third and fourth power supply lines formed in a second wiring layer, extending in a second direction, and connected to the first and second power supply lines, respectively; a fifth power supply line formed in the first wiring layer; and a first power switch circuit including a transistor provided between the first and fifth power supply lines. The transistor overlaps at least one of the third and fourth power supply lines. The first power switch circuit includes first and second wirings formed in the second wiring layer, extending in the second direction, not overlapping the third and fourth power supply lines, and connected to a source of the transistor and the fifth power supply line, and to a drain and the third power supply line, respectively.

Abstract: A display device includes a pixel including a primary inductor and a secondary inductor that are inductively coupled to each other, a pixel circuit electrically connected to the primary inductor, and configured to control a current flowing through the primary inductor by using at least one transistor, and a light emitting unit electrically connected to the secondary inductor, and including at least one light emitting element.

Abstract: A display panel and a fabricating method thereof, and a displaying device. The display panel includes: a driving backplane, a light-emitting-device layer provided on the driving backplane, and a packaging layer, a color-film layer and a light absorbing layer provided on one side of the light-emitting-device layer that is further away from the driving backplane; wherein the light absorbing layer is configured for absorbing light rays of a specific wavelength in external-environment light and in light rays emitted by the light-emitting-device layer; and the specific wavelength includes at least one of a wavelength between a red-light wave band and a green-light wave band, a wavelength between a green-light wave band and a blue-light wave band, a wavelength shorter than a blue-light wave band and a wavelength longer than a red-light wave band.

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

Abstract: A magnetoresistive stack includes a reference layer including a magnetic layer, an antiferromagnetic layer in exchange coupling with the magnetic layer, a magnetic layer substantially of the same magnetisation as the magnetic layer, a spacer layer between the magnetic layers with a thickness for enabling an antiferromagnetic coupling between the magnetic layers of a first coupling intensity, a free layer having a coercivity of less than 10 microTesla, the free layer including a magnetic layer, an antiferromagnetic layer in exchange coupling with the magnetic layer, a magnetic layer substantially of the same magnetisation as the magnetic layer, a spacer layer between the magnetic layers with a thickness for enabling an antiferromagnetic coupling between the magnetic layers of a second coupling intensity lower than the first coupling intensity, a third spacer layer separating the reference and free layers.

Abstract: A semiconductor structure includes a semiconductor substrate and an interconnect structure on the semiconductor structure. The interconnect structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a fourth layer over the third layer. A first through via extends through the semiconductor substrate, the first layer, and the second layer. A second through via extends through the third layer and the fourth layer. A bottom surface of the second through via contacts a top surface of the first through via.

Abstract: The group III nitride semiconductor light emitting element according to this disclosure has, on a substrate, an n-type semiconductor layer, a light emitting layer, a p-type AlGaN electron blocking layer, a p-type contact layer and a p-side reflection electrode, in this order, wherein, a center emission wavelength of light emitted from the light emitting layer is 250 nm or greater and 330 nm or smaller, the Al composition ratio of the p-type AlGaN electron blocking layer is 0.40 or greater and 0.80 or smaller, the film thickness of the p-type contact layer is 10 nm or greater and 50 nm or smaller, and the p-type contact layer has a p-type AlGaN contact layer having Al composition ratio of 0.03 or greater and 0.25 or smaller.

Abstract: A semiconductor high-voltage device includes a semiconductor substrate; a high-voltage well in the semiconductor substrate; a drift region in the high-voltage well; a recessed channel region adjacent to the drift region; a heavily doped drain region in the drift region and spaced apart from the recessed channel; an isolation structure between the recessed channel region and the heavily doped drain region in the drift region; a buried gate dielectric layer on the recessed channel region, wherein the top surface of the buried gate dielectric layer is lower than the top surface of the heavily doped drain region; and a gate on the buried gate dielectric layer.

Abstract: An integrated circuit which includes a GaN FET and a metal-insulator-metal capacitor. The capacitor is fully integrated with a lateral GaN process flow, i.e., the same gate metal layer, field plate metal layer and dielectric layer of the GaN FET are also used to form the bottom plate, insulator and top plate of the capacitor. The top plate is contacted by a conductive via, which extends through the top plate. To increase the voltage breakdown capability of the capacitor of the integrated circuit, a portion of the gate metal layer is formed in the shape of a ring around the conductive via.

Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

Abstract: An embodiment of present invention discloses a light-emitting device which includes a first light-emitting area, a second light-emitting area, and a third light-emitting area. The first light-emitting area emits a red light and includes a first light-emitting unit. The second light-emitting area emits a blue light and includes a second light-emitting unit. The third light-emitting area emits a green light and includes a third light-emitting unit. The first light-emitting area is larger than the second light-emitting area and larger than the third light-emitting area. Each of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit has a width of less than 100 ?m and a length of less than 100 ?m.

Abstract: An optical sensing apparatus including: a substrate including a first material; an absorption region including a second material different from the first material; an amplification region formed in the substrate and configured to collect at least a portion of the photo-carriers from the absorption region and to amplify the portion of the photo-carriers; an interface-dopant region formed in the substrate between the absorption region and the amplification region; a buffer layer formed between the absorption region and the interface-dopant region; one or more field-control regions formed between the absorption region and the interface-dopant region and at least partially surrounding the buffer layer; and a buried-dopant region formed in the substrate and separated from the absorption region, where the buried-dopant region is configured to collect at least a portion of the amplified portion of the photo-carriers from the amplification region.

Abstract: A semiconductor device comprises a substrate that including a frontside comprising an active region and a backside opposite to the frontside, an electronic element on the active region, a frontside wiring structure electrically connected to the electronic element on the frontside of the substrate, and a backside wiring structure electrically connected to the electronic element on the backside of the substrate. The backside wiring structure includes a plurality of backside wiring patterns sequentially stacked on the backside of the substrate, and a super via pattern that intersects and extends through at least one layer of the plurality of backside wiring patterns.

Abstract: Proposed is a MEMS device comprising a layer stack having at least one second layer formed between a first layer and a third layer. At least one first cavity is formed in the second layer. The MEMS device further comprises a laterally deflectable member having an end connected to a sidewall of the first cavity and a free end. Further, the MEMS device includes a passive element rigidly tethered to the free end of the laterally deflectable element to follow movement of the laterally deflectable element. The laterally deflectable element and the passive element divide the first cavity into a first sub-cavity and a second sub-cavity. The first sub-cavity is in contact with an ambient fluid of the MEMS device via at least a first opening. Further, the second subcavity is in contact with the ambient fluid of the MEMS device via at least a second opening. The at least one first opening is formed in a different layer of the first layer and the third layer than the at least one second opening.

Abstract: This disclosure provides a display device, a display panel, and a fabrication method thereof. The display panel includes a driving backplane, a first electrode layer, a pixel definition layer, a light-emitting functional layer, and a second electrode layer. The first electrode layer is arranged on a side surface of the driving backplane and includes a first electrode and a transferring ring. The pixel definition layer covers the first electrode layer and the driving backplane. The light-emitting functional layer is arranged on a surface of the first electrode layer facing away from the driving backplane, and the light-emitting functional layer is in a range of a transferring area of the driving backplane. The second electrode layer covers the pixel definition layer and the light-emitting functional layer. A boundary of the second electrode layer is inside a boundary of the pixel definition layer and is connected with the transferring ring.

Abstract: The present invention relates to the inspection process which includes providing access to the microdevice contacts, measuring the microdevice and analyzing the data to identify defects or performance of the micro device. The invention also relates to the forming of test electrodes on microdevices. The test electrodes may be connected to hidden contacts. The type of microdevices may be vertical, lateral or a flip chip.