Abstract: A header for a semiconductor package includes: an eyelet having an upper surface and a lower surface; a first metal block molded integrally with the eyelet, protruding at the upper surface, and having a substantially U shape; a first lead sealed in a first through hole penetrating the eyelet; a first substrate having a front surface formed with a first signal pattern electrically connected to the first lead and having a back surface fixed to a first end surface of the first metal block; a second lead sealed in a second through hole penetrating the eyelet; and a second substrate having a front surface formed with a second signal pattern electrically connected to the second lead and having a back surface fixed to a second end surface of the first metal block.

Abstract: A semiconductor device includes a gate-all-around field effect transistor (GAA FET). The GAA FET includes channel regions made of a first semiconductor material disposed over a bottom fin layer made of a second semiconductor material, and a source/drain region made of a third semiconductor material. The first semiconductor material is Si1-xGex, where 0.9?x?1.0, and the second semiconductor material is Si1-yGey, where y<x and 0.3?y?0.7.

Abstract: An organic light emitting diode display panel in this disclosure comprises a base substrate, an array layer disposed on the base substrate, and a planarization layer disposed on the array layer. The OLED display panel further comprises anodes disposed on the planarization layer, and a pixel definition layer located between the anodes adjacent to each other. A luminescent layer, a cathode, and an encapsulation layer are provided on the anodes. A preparation material of the pixel definition layer is a light-shading material. By the pixel definition layer made of a light-shading material, the light shading effect of the OLED display panel is greatly enhanced, and the influence of the lateral light leakage of the OLED display panel on the TFT device is prevented.

Abstract: A light emitting device includes: a base; a first terminal and a second terminal located at a surface of the base; a light emitting element array chip mounted on the base, the light emitting element array chip including: a support substrate, a plurality of first wirings and a plurality of second wirings disposed on the support substrate, and a plurality of light emitting elements, each of the light emitting elements arranged on the first wiring and the second wiring and electrically connected to the first wiring and the second wiring; and a plurality of wires including a first wire connecting the first wiring to the first terminal, and a second wire connecting the second wiring to the second terminal.

Abstract: In the embodiments of the present invention, a glass substrate in a micro display panel includes a first surface and a second surface arranged opposite to one another, and a first terminal and a second terminal arranged opposite to one another. An insulation layer disposed on the first surface. A thin film transistor layer disposed on a surface of the insulation layer away from the glass substrate. A micro light-emitting diode layer disposed on a surface of the thin film transistor layer away from the insulation layer. A terminal of the insulation layer, the thin film transistor layer, and the micro light-emitting diode layer close to the first terminal is bent toward a side away from the second surface, and an interval is defined between a terminal of the insulation layer close to the first terminal and the first terminal.

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

Abstract: An organic light-emitting diode (“OLED”) includes a bottom electrode, a top electrode disposed opposite to the bottom electrode, and an organic layer that is interposed between the bottom electrode and the top electrode and includes a hole-transporting host and an electron-transporting host forming an exciplex and a phosphorescent dopant having a triplet energy which is lower than the triplet energy of the hole-transporting host, the triplet energy of the electron-transporting host, and the triplet energy of the exciplex, and a lighting device and a display apparatus including the OLED. Instead of a phosphorescent dopant, the fluorescent dopant having a singlet energy which is lower than the singlet energy of the exciplex may be also used.

Abstract: A display panel and a manufacturing method of a display panel are provided. The display panel includes a display area and a non-display area disposed on one side of the display area. A driving chip and a fanout wiring area are disposed in the non-display area. A fanout line module is disposed in the fanout wiring area. The fanout line module includes a first wiring area and a second wiring area. A first signal line connecting the data line is disposed in the first wiring area. A second signal line connecting the gate line and another first signal line connecting the data line are disposed in the second wiring area.

Abstract: The present disclosure is directed to methods for producing a photovoltaic junction that can include coating a bare junction with a composition. In one embodiment, the composition includes a plurality of quantum dots to create a film; exposing the film to a ligand to create a first layer; coating the first layer with the composition to form a film on the first layer; and exposing the film on the first layer to the ligand to create a second layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, and a side surface between the first and second surfaces, and including a device region on the first surface a wiring structure on the surface of the semiconductor substrate, and having a dielectric layer and a metal wiring in the dielectric layer and electrically connected to the device region, and an insulating material layer on a side surface of the wiring structure and having a side surface connected to the side surface of the semiconductor substrate. The side surface of the insulating material layer has a first wave-shaped pattern in which concave-convex portions are repeated in a direction of the wiring structure that is perpendicular to the semiconductor substrate, and the side surface of the semiconductor substrate has a second wave-shaped pattern in which concave-convex portions are repeated in the direction.

Abstract: Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.

Abstract: The present inventive concept relates to a display device. A display device according to an exemplary embodiment of the present inventive concept include: a base layer including a plurality of islands in which a pixel is disposed, a plurality of bridges disposed around each of the plurality of islands, a plurality of first wires disposed in a bridge of the plurality of bridges connected to the pixel is disposed; an inorganic insulating layer disposed on the base layer and having an opening exposing a portion of the bridge; and an organic material layer covering the opening, wherein adjacent islands of the plurality of islands are connected to each other through at least the bridge of the plurality of bridges, and the plurality of first wires are disposed on the organic material layer.

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

Abstract: In general aspect, a semiconductor device package can include a substrate and a semiconductor die disposed on and coupled with the substrate. The semiconductor device package can further include a leadframe having an indentation defined therein, at least a portion of the indentation being disposed on and coupled with the semiconductor die via a conductive adhesive.

Abstract: Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.

Abstract: Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The multiple transistors may include multiple P-type transistors that are arranged in a P-over-P stack configuration, and the multiple transistors may include multiple N-type transistors that are arranged in an N-over-N stack configuration.

Abstract: A semiconductor package includes a semiconductor die, an encapsulant, a first and second dielectric layer, a through via, an extension pad, and a routing via. The semiconductor die includes a contact post. The first dielectric layer extends on the encapsulant. The through via extends through the first dielectric layer and has one end contacting the contact post. The extension pad is disposed on the first dielectric layer, contacting an opposite end of the through via with respect to the contact post. The extension pad has an elongated shape, a first end of the extension pad overlaps with the contact post and the through via, and a second end of the extension pad overlaps with the encapsulant. The second dielectric layer is disposed on the first dielectric layer and the extension pad. The routing via extends through the second dielectric layer to contact the second end of the extension pad.

Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

Abstract: The present disclosure belongs to the technical field of integrated circuit packaging, and specifically relates to a through silicon via structure for three-dimensional integrated circuit packaging and a manufacturing method thereof.

Abstract: Disclosed is a low temperature method of fabrication of short-wave infrared (SWIR) detector arrays (FPA) including a readout wafer and absorption layer connected for improved performances. The absorber layer includes a SWIR conversion layer with a GeSn or SiGeSn alloy. A first series of process steps realizes a CMOS processed readout wafer. A buffer layer is transferred on the readout wafer and annealed at temperatures compatible with the CMOS substrate, achieving a high quality crystalline buffer layer. The method assures a temperature profile between the light entrance surface of the buffer layer, and the readout electronics so the annealing temperature remains compatible with the CMOS. The buffer layer is used for further growth of a GeSn or SiGeSn structure to create the conversion layer and achieve the final structure of the SWIR FPA. Also disclosed is a SWIR FPA detector as realized by such method, and SWIR FPA applications.