Patents Examined by Hewy H Li
  • Patent number: 10802720
    Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 13, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Chin-Pang Chang, Chun-Yi Lo
  • Patent number: 10783086
    Abstract: A method for accessing data is provide, the method includes: receiving a first address and identification information used to identify an address type; and when the identification information indicates a logical address type, converting the first address into a first physical address, and accessing at least one corresponding flash memory chip in the storage device; or when the identification information indicates a physical address type, directly accessing at least one corresponding flash memory chip in the storage device. When the storage device is accessed, a type of an accessed address is determined according to the identification information. If the address is a logical address, the storage controller maps the logical address to a physical address and accesses the physical address; or if the address is a physical address, the storage controller directly accesses the physical address sent by the host.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: September 22, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jie Zhou, Guanghui Liu, Weiye Zhang
  • Patent number: 10776148
    Abstract: Disclosed are systems and methods for parallel processing an input data set. During a map stage of a computation, starting with a first virtual machine (VM) acting as a parent VM and an input data set, the system clones the parent VM to generate at least one linked clone child VM. The system further divides the input data set into a first chunk for the parent VM and a second chunk for the at least one child VM by determining a starting pointer for each chunk. Each chunk is processed by a VM to generate an intermediate data result, which is stored in a network storage device. The plurality of VMs then perform a reduce stage on the plurality of intermediate data results stored in the network storage device.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: September 15, 2020
    Assignee: Parallels International GmbH
    Inventors: Anton Zelenov, Nikolay Dobrovolskiy, Serguei M. Beloussov
  • Patent number: 10776038
    Abstract: In one embodiment, a system includes one or more processors and a memory storing instructions that, when executed by the one or more processors, cause the one or more processors to perform operations including sequencing a plurality of rows into a first sequence based on a first criteria and determining to store a first set of the plurality of rows in a first block of a first storage unit in accordance with the first sequence. The operations further include determining to store, in a first block of the second storage unit, a block identification of the first block of the first storage unit and a row identification for each row of the first set of the plurality of rows. The operations further include re-creating the first set of the plurality of rows of the first block of the first storage unit using information stored in the second storage unit.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: September 15, 2020
    Assignee: Bank of America Corporation
    Inventor: Sandeep Verma
  • Patent number: 10761985
    Abstract: Circuits and methods for combined precise and imprecise snoop filtering. A memory and a plurality of processors are coupled to the interconnect circuitry. A plurality of cache circuits are coupled to the plurality of processor circuits, respectively. A first snoop filter is coupled to the interconnect and is configured to filter snoop requests by individual cache lines of a first subset of addresses of the memory. A second snoop filter is coupled to the interconnect and is configured to filter snoop requests by groups of cache lines of a second subset of addresses of the memory. Each group encompasses a plurality of cache lines.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 1, 2020
    Assignee: Xilinx, Inc.
    Inventors: Millind Mittal, Jaideep Dastidar
  • Patent number: 10747659
    Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a memory controller or similar device for storing sequential image data or other data streams composed of pages of data. In one example, the memory controller compares data within current and previous image frames on a page-by-page basis. If a pair of pages match, the memory controller creates a link between the two pages so the duplicate page need not be stored. During a subsequent read operation, the flash controller accesses stored links to identify the physical storage addresses of any matching pages stored in connection with a previous frame to permit efficient retrieval. In some examples, a page is compared with both the previous corresponding page and with the neighboring pages of that previous page. Exemplary read, write and erase operations are described herein using the links.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Weijie Yu, Rohit Sehgal, Zachary David Shepard
  • Patent number: 10740032
    Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 11, 2020
    Assignee: Arm Limited
    Inventors: Chiranjeev Acharya, Sean James Salisbury, Eduard Vardanyan, Arthur Brian Laughton
  • Patent number: 10719237
    Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh Sundaram, Derchang Kau, Owen W. Jungroth, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami
  • Patent number: 10719401
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a write request which includes data, and allocating an inode entry in a central inode list, such that the inode entry corresponds to the data received. The data is allocated to a block of storage space in memory. Moreover, one or more instructions to write the data to the block of storage space are sent. A determination is also made as to whether the data fills a threshold amount of a last block of storage space. In response to determining that the data does not fill the threshold amount of the last block of storage space, one or more instructions to create an identifier at an end of the data are sent. Furthermore, one or more instructions to store a copy of the inode entry after the identifier in the last block of storage space are sent.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: July 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Itzhack Goldberg, Deborah A. Messing
  • Patent number: 10712943
    Abstract: A memory monitoring and selective defragmentation method and system disclosed herein monitor memory usage by and modification of one or more database indexes. The monitoring and selective defragmentation method and system selectively defragment the one or more database indexes based on memory cost savings as opposed to a percentage of fragmentation to improve performance of databases.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: July 14, 2020
    Assignee: IDERA, INC.
    Inventor: Vicky Harp
  • Patent number: 10678436
    Abstract: A storage system performs garbage collection with data compression. A storage controller in the storage system determines a garbage collection directive by evaluating the amount of reclaimable space relative to a target amount of reclaimable space. Garbage collection is performed using data compression tunable to compression aggressiveness according to the garbage collection directive.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: June 9, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Yanwei Jiang, Aswin Karumbunathan, Naveen Neelakantam, Kiron Vijayasankar, Bo Feng, Joern Engel
  • Patent number: 10671291
    Abstract: Example implementations relate to memory read requests. For example, an implementation may include tracking progress of an iterative write sequence to write data to a memory element of a memory module. A received read request is detected to be addressed to a memory bank that includes the memory element undergoing the iterative write sequence. Based on the tracked progress, a time is determined to interrupt the iterative write sequence with insertion of the read request. The time aligns between operations of the iterative write sequence and data is returned within a predetermined read latency.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: June 2, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B Lesartre, Martin Foltin
  • Patent number: 10664185
    Abstract: A computer-implemented method according to one embodiment includes identifying an extent to be relocated within a storage environment, determining a current workload of each of a plurality of storage drives within the storage environment, determining current performance capabilities of each of a plurality of backend storage controllers associated with the plurality of storage drives within the storage environment, and moving the extent to one of the plurality of storage drives, based on the current workload for each of the plurality of storage drives and the current performance capabilities of the plurality of backend storage controllers.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kushal S. Patel, Shalaka Verma, Mohit Chitlange, Sarvesh S. Patel
  • Patent number: 10656855
    Abstract: A memory manager on a programmable device manages memory allocated to accelerators on the programmable device and allocated to processes that access the programmable device. The memory manager can manage both memory on the programmable device as well as external memory coupled to the programmable device. The memory manager protects the memory from unauthorized access by enforcing protection for the memory, using keys, encryption or the like. The memory manger can allocate a partition of memory to an accelerator when an accelerator is deployed to a programmable device, then allocate subpartitions within the allocated partition for each process that accesses the accelerator. When an accelerator is cast out of the programmable device, the memory partition is scrubbed so it can be reclaimed and allocated to another accelerator. When a process terminates, the subpartitions corresponding to the process are scrubbed so they may be reclaimed and allocated to another process.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Paul E. Schardt, Jim C. Chen, Lance G. Thompson, James E. Carey
  • Patent number: 10642509
    Abstract: A method for controlling operations of a data storage device, the associated data storage device and the controller thereof are provided. The method can comprise: selecting a block of multiple blocks of a non-volatile (NV) memory element of a plurality of NV memory elements; receiving a data-writing command from a host device; generating a plurality of operating commands corresponding to the data-writing command, and sending the plurality of operating commands to the NV memory to perform data-writing on a plurality of non-reserved word-lines of the block, wherein the block comprises the plurality of non-reserved word-lines and a plurality of reserved word-lines, and each non-reserved word-line of the plurality of non-reserved word-lines comprises multiple pages; and writing user data into a reserved word-line of the plurality of reserved word-lines through a single level cell (SLC) writing mode, to make the reserved word-line comprise a single page.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: May 5, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Sheng-Liu Lin
  • Patent number: 10642328
    Abstract: A solid state drive with a reset circuit includes a controlling circuit, a flash array and a buffer. The controlling circuit includes a physical layer circuit and a first input/output port. The first input/output port is connected with a first reset terminal of a host. The flash array and the buffer are connected with the controlling circuit. When the first reset terminal of the host activates a reset signal, a voltage level of the first input/output port is changed. After a delay time, the voltage level of a second reset terminal of the physical layer circuit is changed and the physical layer circuit is reset.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: May 5, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: I-Hsiang Chiu, Shih-Hung Hsieh
  • Patent number: 10642695
    Abstract: Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventors: James E. Dunn, Nathan A. Eckel
  • Patent number: 10628063
    Abstract: A method and device generates a slab identifier and a hash function identifier in response to a memory allocation request with a request identifier and allocation size from a memory allocation requestor. The slab identifier indicates a memory region associated with a base data size and the hash function identifier indicates a hash function. The method and device provides a bit string including the slab identifier and the hash function identifier to the memory allocation requestor.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 21, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Alexander Dodd Breslow
  • Patent number: 10593305
    Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller. The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 17, 2020
    Assignee: Arm Limited
    Inventors: Michal Karol Bogusz, Damian Piotr Modrzyk, Quinn Carter, Thomas James Cooksey
  • Patent number: 10585792
    Abstract: A data processing system includes a host suitable for providing an access request; and a plurality of memory systems suitable for storing or reading data thereto or therefrom in response to the access request, wherein the host includes a host memory buffer suitable for storing a plurality of meta-data respectively corresponding to the plurality of memory systems, wherein each of the plurality of meta-data includes a first threshold value representing storage capacity for user data in a corresponding memory system among the plurality of memory systems, a second threshold value representing a number of read operations for logical block addresses (LBAs) of the corresponding memory system, a third threshold value representing a temperature of the corresponding memory system and respective LBAs of the plurality of memory systems.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 10, 2020
    Assignee: SK hynix Inc.
    Inventors: Soong-sun Shin, Duck-Hoi Koo, Yong-Tae Kim, Cheon-Ok Jeong