Patents Examined by Hewy H Li
  • Patent number: 11151057
    Abstract: A method for managing data includes generating, by an offload device, predicted active logical partition data using an active logical partition mapping obtained from a host computing device, generating logical partition correlation data using active memory track maps obtained from the host computing device, generating most probable tracks using the predicted active logical partition data and the logical partition correlation data, and sending the most probable tracks to the host computing device, wherein the host computing device evicts data from a memory device based on the most probable tracks.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: October 19, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jonathan I. Krasner, Jason Jerome Duquette
  • Patent number: 11132144
    Abstract: An integrated interface for an electronic device without a USB port includes at least one SIM card interface drive chip, a USB interface control chip, at least one SIM card interface control chip electronically connected to the at least one SIM card interface drive chip and the USB interface control chip, and a USB interface drive chip electronically connected to the USB interface control chip. A detection signal pin is defined on the USB interface control chip. When the detection signal pin is triggered, the USB interface control chip is turned on and the SIM card interface drive chip is turned off. When triggered, the USB interface drive chip drives the USB interface control chip to work, allowing access by an external whole-machine probe or test device.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 28, 2021
    Assignees: Fu Tai Hua Industry (Shenzhen) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Cheng-Xiang Liu
  • Patent number: 11106591
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: August 31, 2021
    Assignee: Texas Instmments Incorporated
    Inventor: Joseph Zbiciak
  • Patent number: 11086793
    Abstract: Techniques for cache management may include: partitioning a cache into buckets of cache pages, wherein each bucket has an associated cache page size and each bucket includes cache pages of the associated cache page size for that bucket, wherein the cache includes compressed pages of data and uncompressed pages of data; and performing processing that stores a first page of data in the cache. The processing may include storing the first page of data in a first cache page of a selected bucket having a first associated cache page size determined in accordance with a first compressed size of the first page of data. The cache may be repartitioned among the buckets based on associated access frequencies of the buckets of cache pages.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 10, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Anton Kucherov, David Meiri
  • Patent number: 11086526
    Abstract: The present disclosure provides techniques for implementing a computing system that includes a processing sub-system, a memory sub-system, and one or more memory controllers. The processing sub-system includes processing circuitry that performs an operation based on a target data block and a processor-side cache coupled between the processing circuitry and a system bus. The memory sub-system includes a memory that stores data blocks in a memory array and a memory-side caches coupled between the memory channel and the system bus. The one or more memory controllers control caching in the processor-side cache based at least in part on temporal relationship between previous data block targeting by the processing circuitry and control caching in memory-side cache based at least in part on spatial relationship between data block storage locations in the memory channel.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Anton Korzh, Stephen S. Pawlowski
  • Patent number: 11074131
    Abstract: Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James E. Dunn, Nathan A. Eckel
  • Patent number: 11074099
    Abstract: A system and method receiving a request to transfer first data from a first storage space to a second storage space, receiving a write request to write second data to a location during the transfer of the first data, determining from an access data structure that the location is not in use, writing the second data to the second storage space, and updating a location data structure indicating the location of the second data to be in the second storage space.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 27, 2021
    Assignee: Nutanix, Inc.
    Inventors: Felipe Franciosi, Peter Turschmid, Malcolm Crossley
  • Patent number: 11073995
    Abstract: A method and device generates a slab identifier and a hash function identifier in response to a memory allocation request with a request identifier and allocation size from a memory allocation requestor. The slab identifier indicates a memory region associated with a base data size and the hash function identifier indicates a hash function. The method and device provides a bit string including the slab identifier and the hash function identifier to the memory allocation requestor.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: July 27, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Alexander Dodd Breslow
  • Patent number: 11068394
    Abstract: Provided is a neural network system for processing data transferred from an external memory. The neural network system includes an internal memory storing input data transferred from the external memory, an operator performing a multidimensional matrix operation by using the input data of the internal memory and transferring a result of the multidimensional array operation as output data to the internal memory, and a data moving controller controlling an exchange of the input data or the output data between the external memory and the internal memory. The data moving controller reorders a dimension order with respect to an access address of the external memory to generate an access address of the internal memory, for the multidimensional matrix operation.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 20, 2021
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeongmin Yang, Young-Su Kwon
  • Patent number: 11061588
    Abstract: A computer-implemented method according to one embodiment includes receiving a request to add a generic volume entry to a generic volume element list, storing the generic volume entry in the generic volume element list in a SMS configuration in a SCDS, and building a volume list definition of the SMS configuration. A unit control block chain is parsed for determining additional specific volumes. It is determined whether a specific volume found in the parsing was not used in the building. In response to a determination that the specific volume found in the parsing was not used in the building, it is determined, for the specific volume found in the parsing, whether at least one predetermined condition is met. The specific volume found in the parsing is added to the volume list definition in response to a determination that the at least one predetermined condition is met.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Tan Q. Nguyen, Gerard Maclean Dearing, Andrew Trinh, Romell Williams, Wilson Yang, Jwu-Shyan Tarng
  • Patent number: 11061587
    Abstract: According to one embodiment, the memory system includes a memory and a memory controller. After the memory controller determines that a plurality of first commands including addresses have been received from a host device in a first sequence, when a plurality of second commands including addresses are received from the host device in a second sequence, the memory controller stores the addresses included in the plurality of the second commands in a memory; converts the address stored in the memory into a first password; and restricts or does not restrict execution of the first command and the second command from the host device after the memory system is started up, and removes the restriction of the execution or restricts the execution of the first command and the second command from the host device after the first password is matched with a predetermined second password.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 13, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Matsukawa
  • Patent number: 11042325
    Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 22, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jie Zheng, Steven R. Carlough, William J. Starke, Jeffrey A. Stuecheli, Stephen J. Powell
  • Patent number: 11036429
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The memory control method includes: determining a first management unit as a source block and reading valid data from a first continuous data unit in the first management unit according to first interleaving information and second interleaving information, wherein the first interleaving information reflects a total number of the first continuous data units in the first management unit, and the second interleaving information reflects a total number of second continuous data units in a second management unit; storing the valid data into a recycling block; and erasing the first management unit.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: June 15, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Che-Yueh Kuo, Wei-Jeng Wang
  • Patent number: 11023158
    Abstract: Embodiments of the present disclosure provide a method, apparatus, and computer program product for storing data. A method for storing data comprises: dividing data to be stored into a first number of data segments; generating a second number of coding segments based on the first number of data segments, such that at least a part of data segments from the first number of data segments can be derived from the second number of coding segments and remaining data segments in the first number of data segments; generating, for each of the first number of data segments, a replication data segment identical to the data segment; and storing the first number of data segments, the first number of replication data segments and the second number of coding segments into a plurality of storage devices. Embodiments of the present disclosure can reduce extra overhead for protecting data while ensuring high data availability.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 1, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Ao Sun, Gary Jialei Wu, Lu Lei
  • Patent number: 11023152
    Abstract: When storing an array of data in memory, the data array is divided into a plurality of blocks, and for respective groups of the blocks that the data array has been divided into, a set of data representing the group of blocks that includes: for each block of the group of blocks, a set of data for that block of the group of blocks; and a size indication for each of one or more of the blocks of the group of blocks, the size indication for a block of a group of blocks indicating the size in memory of the set of data for that block of the group included in the stored set of data representing the group of blocks, is stored. A set of header data is also stored separately for each group of blocks of the data array.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: June 1, 2021
    Assignee: Arm Limited
    Inventors: Jorn Nystad, Edvard Fielding, Jakob Axel Fries
  • Patent number: 11003357
    Abstract: Communications between a host system and a storage system may be restricted to a single I/O path, at least temporarily, without manually manipulating physical connections to the host system and/or storage system or manually data structures defining I/O connectivity. In response to a communication to maintain only a first permitted I/O path between a host system and a storage system, I/O communications may be prevented on any I/O paths between the host system and the storage system, except for the first permitted I/O system, without modifying the definition of any permitted I/O paths on the storage system. One or more fields may be included in entries of a data structure that defines permitted I/O paths, the fields specifying whether an I/O path should be allowed to, or prevented from, carry communications between a host system and the storage system, at least temporarily.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: May 11, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Owen Crowley, Scott Rowlands, Vinay G. Rao, Arieh Don
  • Patent number: 11003376
    Abstract: A solid state drive (SSD) includes a first storage region classified as byte addressable NV storage region and a controller communicatively coupled to the first storage region by a bus. The controller detects a reduced storage capacity of the first storage region, and in response to the detection, reclassifies the first storage region as a block addressable NV storage region. The SSD dynamically changes byte addressable NV storage regions to block addressable NV storage regions as the byte addressable NV storage regions are degraded, thereby extending the longevity of the SSD.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: May 11, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Edward Xiao, Scott Stetzer
  • Patent number: 10996872
    Abstract: Provided are a memory device and a memory system. A memory device which is connected to the channel, comprises a memory cell array and a memory-authority control unit which controls operational authority of the channel, wherein the memory device controls data flow of other memory device connected to the channel, when the memory-authority control unit has the operational authority of the channel.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 4, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young Geun Choi
  • Patent number: 10997077
    Abstract: A data structure (e.g., a table) stores a listing of prefetches. Each entry in the data structure includes a respective virtual address and a respective prefetch stride for a corresponding prefetch. If the virtual address of a memory request (e.g., a request to load or fetch data) matches an entry in the data structure, then the value of a counter associated with that entry is incremented. If the value of the counter satisfies a threshold, then the lookahead amount associated with the memory request is increased.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: May 4, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: David Carlson
  • Patent number: 10990305
    Abstract: A storage apparatus includes: a plurality of controllers, each of which has a plurality of processors for processing requests; a storage device coupled to the controller; an integration unit that integrally controls the plurality of controllers; and a shared memory that can be accessed from each processor for the plurality of controllers and stores configuration information of the storage apparatus including load information of each processor. The integration unit: calculates estimated processing time of a configuration management request, which has been accepted from a management apparatus, from a request type and a target resource type of the configuration management request; and distributes the configuration management request to a plurality of distribution requests on the basis of the load information of each processor acquired from the shared memory and the estimated processing time, determines a distribution destination processor for processing each of the plurality of distribution requests.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 27, 2021
    Assignee: HITACHI, LTD.
    Inventors: Ryosuke Yabu, Shinichiro Kanno