Patents Examined by Hewy H Li
  • Patent number: 11327939
    Abstract: A method for indexing dirty data in a storage system page includes: obtaining a point quantity of storage points in the storage page and dirty data distribution information; creating a bitmap based on the point quantity and dirty data distribution information; creating an extended segment set based on the dirty data distribution information, and obtaining the number of current extended segments in the extended segment set; obtaining, according to the point quantity, a first storage cost for indexing dirty data using the bitmap in the target storage page; obtaining, according to the number of current extended segments and the segment capacity, a second storage cost for indexing dirty data using the extended segments in the target storage page; and determine, according to the first storage cost and the second storage cost, to index the dirty data in the target storage page by means of the bitmap or the extended segments.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: May 10, 2022
    Assignee: ZTE CORPORATION
    Inventors: Shengmei Luo, Jiwu Shu, Youyou Lu, Hongzhang Yang
  • Patent number: 11327889
    Abstract: The invention relates to a method for managing a buffer memory space associated with a persistent data storage system of a computing machine. The buffer memory space is suitable for temporarily storing in the RAM of the machine one or more portions of a single data file of the persistent data storage system that was previously accessed by one or more processes executed on the machine. The operating system of the machine tracks each of the portions of the file that are projected in the buffer memory space by a descriptor belonging to a plurality of buffer memory projection descriptors which are all associated with the tracking of one or more portions of the file projected in the buffer memory space.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: May 10, 2022
    Assignee: BULL SAS
    Inventors: Jean-Olivier Gerphagnon, Frédéric Saunier, Grégoire Pichon
  • Patent number: 11321273
    Abstract: A distributed storage system including memory hosts and at least one curator in communication with the memory hosts. Each memory host has memory, and the curator manages striping of data across the memory hosts. In response to a memory access request by a client in communication with the memory hosts and the curator, the curator provides the client a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 3, 2022
    Assignee: Google LLC
    Inventors: Kyle Nesbit, Andrew Everett Phelps
  • Patent number: 11314460
    Abstract: A solid state drive (SSD) enabled to process and store block addressable and byte addressable data, includes a first storage region for storing byte addressable data, a second storage region for storing block addressable data, and an SSD controller coupled to the first storage region and the second storage region by a bus. The SSD controller includes a processor and an interface for receiving data packets from a host. The SSD controller receives a data packet from the host at the interface, determines whether the data packet includes byte addressable data or block addressable data at the processor, selects either the first storage region or the second storage region based on the determination, and stores the data associated with the data packet in the selected storage region.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: April 26, 2022
    Assignee: Kioxia Corporation
    Inventors: Edward Xiao, Scott Stetzer
  • Patent number: 11307990
    Abstract: Implementations of the present specification provide a method for deploying a smart contract. According to one implementation the method includes: receiving a transaction request for invoking a first contract; obtaining a first instruction code and a function index table, wherein the function index table is used to indicate a memory address of an instruction code corresponding to each of import and export functions in the first contract; determining a first memory address corresponding to the invocation function based on the function index table; and executing the first instruction code in the first memory address based on the determined first memory address.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: April 19, 2022
    Assignee: Advanced New Technologies Co., Ltd.
    Inventor: Zhongxiao Yao
  • Patent number: 11301378
    Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: April 12, 2022
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Christopher Haywood
  • Patent number: 11294817
    Abstract: To perform a lookup for a group of plural portions of data in a cache together, a first part of an identifier for a first one of the portions of data in the group is compared with corresponding first parts of the identifiers for cache lines in the cache, the first part of the identifier for the first one of the portions of data in the group is compared with the corresponding first parts of the identifiers for the remaining portions of data in the group of plural portions of data, and a remaining part of the identifier for each portion of data is compared with the corresponding remaining parts of identifiers for cache lines in the cache. It is then determined whether a cache line for any of the portions of data in the group is present in the cache, based on the results of the comparisons.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: April 5, 2022
    Assignee: Arm Limited
    Inventor: Antonio Garcia Guirado
  • Patent number: 11288196
    Abstract: In response to receiving a read metadata request from the host system for a data portion, the storage system may determine a status and location of the data portion, including determining whether the data portion is in a cache of the storage system. If the data portion is in the cache, the storage system may send a response that includes the data portion itself along with the status and location of the data portion. If the data portion is not in the cache, the storage system may send a response to the read metadata request that includes the status and location of the data portion, but not the data portion itself. The host system may be configured to determine whether the data portion has been returned with the metadata response, and if so, refrain from sending a separate data request, for example, to retrieve the data portion from cache.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: March 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Gabriel Benhanokh, Ian Wigmore, Arieh Don
  • Patent number: 11269561
    Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Jie Zheng, Steven R. Carlough, William J. Starke, Jeffrey A. Stuecheli, Stephen J. Powell
  • Patent number: 11263125
    Abstract: A method can be used for managing a memory circuit that includes memory sectors having respective positions in the memory circuit as well as respective addresses for data transfer transactions. The method includes maintaining a record of coupling pairs of the positions and the addresses. Each coupling pair includes a memory sector in the plurality of memory sectors and an address coupled with the memory sector for data transfer transactions with respect to the memory sector. The method also includes keeping counts of the data transfer transactions involving the memory sectors in the plurality of memory sectors and replacing a first memory sector included in a coupling pair and having a first count of transactions with a second memory sector having a second count of transactions as a result of a condition being met.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 1, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Alberto Saviotti
  • Patent number: 11256628
    Abstract: A distributed storage system comprises a first module and a second module. The first module processes read requests for an address range, to send to the second module. The first module receives an address associated with a read request for a data page stored on the second module. A method searches a table on the first module for a content-based signature of the data page based on the address and provides the data page from a first module read cache if the content-based signature is in the read cache, where content-based signatures in the table are associated with the address range.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: February 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: David Meiri, Anton Kucherov
  • Patent number: 11249686
    Abstract: A controller for controlling a memory device includes: a command queue suitable for queuing two or more commands received from a host; a re-generation queue suitable for queuing, in response to an abort command for aborting an abort-target command, a re-generated command corresponding to a remaining command other than the abort-target command among the commands queued in the command queue; a processor suitable for resetting the command queue when queuing a command in the re-generation queue is completed, and queuing the re-generated command into the command queue.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: February 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Kiduck Kim, Wonkyoo Lee
  • Patent number: 11249911
    Abstract: A memory system includes a storage device including a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device, and a host that accesses the storage device. The storage device transfers map data, in which a physical address of the nonvolatile memory device and a logical address provided from the host are mapped, to the host depending on a request of the host. The host stores and manages the transferred map data as map cache data. The map cache data are managed depending on a priority that is determined based on a corresponding area of the nonvolatile memory device.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: February 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Woo Kim, Dongin Kim, Songho Yoon, Youngjoon Jang, Wookhan Jeong
  • Patent number: 11237970
    Abstract: A computing system, method and apparatus to cache a portion of a data block. A processor can access data using memory addresses in an address space. A first memory can store a block of data at a block of contiguous addresses in the space of memory address. A second memory can cache a first portion of the block of data identified by an item selection vector. For example, response to a request to cache the block of data stored in the first memory, the computing system can communicate the first portion of the block of data from the first memory to the second memory according to the item selection vector without accessing a second portion of the block of data. Thus, different data blocks in the first memory of a same size can be each cached in different cache blocks of different sizes in the second memory.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 11237973
    Abstract: A memory system includes a memory device and a controller. The memory device stores a piece of data in a location which is distinguished by a physical address. The controller generates map data, each piece of map data associating a logical address, inputted along with a request from an external device, with the physical address, selects a piece of map data among the map data based on a status regarding the piece of map data, and transfers selected map data to the external device.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Hye-Mi Kang, Eu-Joon Byun, Byung-Jun Kim, Seok-Jun Lee
  • Patent number: 11232038
    Abstract: A ternary content addressable memory device (TCAM) may include: a cache memory storing a look-up table with respect to a calculation result of a plurality of functions; an approximation unit configured to generate mask bits; and a controller configured to obtain an approximation input value corresponding to an input key based on the mask bits and to retrieve an output value corresponding to the obtained approximation input value from the look-up table.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: January 25, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ihor Vasyltsov, Youngnam Hwang, Yongha Park
  • Patent number: 11216195
    Abstract: An allocation history is maintained for each node in a multi-node data storage system. The allocation history for each node indicates sets of physical blocks previously allocated to the node to store dirty pages of user data flushed from a cache of the node. The allocation history indicates non-quarantined sets of physical blocks that are currently being used to provide non-volatile data storage to cache flush operations, and quarantined sets of physical blocks not currently being used to provide non-volatile data storage to cache flush operations. Allocation is prevented to any node of any set of physical blocks that is indicated as non-quarantined by any of the allocation histories, and of any set of physical blocks that is indicated as quarantined by any of the allocation histories.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: January 4, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Vamsi K. Vankamamidi, Bruce E. Caram, Ajay Karri
  • Patent number: 11210227
    Abstract: A method for demoting data from a cache comprising heterogeneous memory types is disclosed. The method maintains, for a data element in the cache, a write access count that is incremented each time the data element is updated in the cache. The cache includes a higher performance portion and a lower performance portion. The method removes the data element from the higher performance portion in accordance with a cache demotion algorithm. If the data element also resides in the lower performance portion and the write access count is below a first threshold, the method leaves the data element in the lower performance portion. If the data element also resides in the lower performance portion and the write access count is at or above the first threshold, the method removes the data element from the lower performance portion. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kyler A. Anderson, Kevin J. Ash
  • Patent number: 11188455
    Abstract: A computer-implemented method can include obtaining tape data for one or more tapes. The tape data can include pointer data corresponding to a first file. The method can further include determining, based on the tape data, that the first file is stored on a first tape of the one or more tapes. The first tape can have an export status. The method can further include determining that the pointer data includes a pointer to the first tape and a pointer to a second tape. The second tape can have a non-export status. The method can further include storing at least a portion of the tape data. The method can further include initiating, based on the first tape having the export status, a deactivation of the pointer to the first tape.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hiroshi Araki, Hiroyuki Miyoshi
  • Patent number: 11175849
    Abstract: In one embodiment, a system includes one or more processors and a memory storing instructions that, when executed by the one or more processors, cause the one or more processors to perform operations including sequencing a plurality of rows into a first sequence based on a first criteria and determining to store a first set of the plurality of rows in a first block of a first storage unit in accordance with the first sequence. The operations further include determining to store, in a first block of the second storage unit, a block identification of the first block of the first storage unit and a row identification for each row of the first set of the plurality of rows. The operations further include re-creating the first set of the plurality of rows of the first block of the first storage unit using information stored in the second storage unit.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: November 16, 2021
    Assignee: Bank of America Corporation
    Inventor: Sandeep Verma