Abstract: A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

Abstract: A segmented ultrasound body suit having a suit assembly with a plurality of separated segments having a torso and buttocks segment, a pair of mirror image arm segments, a pair of mirror image thigh segments, and a pair of mirror image calf segments. A plurality of cutouts is disposed in the segments. Each cutout is affixed within with a pad containing a power source and a switched ultrasound transducer and pressure switch. An ultrasound energy is transferred to a skin contact surface by a plate housed within the pad. A user dons any or all segments for chosen ultrasound treatment, with choice of off and on at each pad.

Abstract: The invention provides methods for intraoperatively determining the location of nerves by use of fluorescent dyes. The methods are particularly useful for locating the cavernous nerves innervating the penis.

Abstract: According to some embodiments herein, systems for delivering therapeutic agents and/or methods of using such systems are provided. The systems can be configured to administer solution comprising therapeutic agent to a subject, and can further comprise an ultrasound applicator for applying ultrasound energy to the subject.

Abstract: A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops.

Abstract: Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

Abstract: Systems and methods for providing therapeutic shock waves are provided. A modified acoustic lens can include a first lens portion for directing a first part of an acoustic shock wave pulse toward a target and a second lens portion for directing a second part of the acoustic shock wave pulse toward the target. The second lens portion can be offset relative to the first portion such that transmission of the second part of the acoustic shock wave pulse through the second lens portion is delayed by a predetermined amount relative to transmission of the first part through the first lens portion. In situ superposition of the first and second pulses near and at the target can lead to the formation of a pressure waveform with idealized pulse profile and broadened focal width, which can provide for improved comminution of a concretion located within a living body with reduced tissue injury.

Abstract: Embodiments of the present disclosure generally relate to non-volatile memory and, in particular, non-volatile memory with adjustable cell bit shapes. In one embodiment, an adjustable memory cell is provided. The memory cell generally includes a gate electrode, at least one recording layer and a channel layer. The channel layer generally is capable of supporting a depletion region and is disposed between the gate electrode and the at least one recording layer. In this embodiment, upon activating the gate, the channel layer may be depleted and current initially flowing through the channel may be steered through the at least one recording layer.

Abstract: Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A refresh operation is then performed on at least one selected row of memory in the memory system based on the randomly-chosen seed row. Additional apparatuses and methods are described.

Abstract: A device for thrombolytic therapy is provided. The device includes an elongate catheter with a distal end portion and a proximal end portion and a first lumen extending through both distal and proximal end portions. The distal end portion of the catheter includes an echogenic tubular potion that defines or surrounds a portion of the first lumen. An expandable balloon coaxially surrounds the tubular portion. The tubular portion additionally includes a plurality of indentations defined upon an outer surface thereof.

Abstract: A system and method for adjusting or selecting the treatment parameters for HIFU signals to treat a target treatment site, and/or to aid in visualizing the likely degree and location of HIFU effects on patient tissue. The system transmits one or more test signals into patient tissue and receives signals created in response to the test signals. The signals are analyzed to determine a response curve of how a characteristic of the signal varies with the one or more test signals. The response curve of the detected signals is used to select a treatment parameter.

Abstract: Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.

Abstract: Data corrupted by a soft error is recovered. A storage device includes a first memory cell, a second memory cell, a sense circuit electrically connected to the first memory cell through a first sense line and to the second memory cell through a second sense line, a digital-analog converter circuit electrically connected to the first memory cell and the second memory cell through a bit line, and an analog-digital converter circuit. The digital-analog converter circuit has a function of applying voltages as first signals to the first memory cell and the second memory cell. Even when a soft error occurs in the first memory cell or the second memory cell, the storage device has a function of recovering data corrupted by the soft error because the sense circuit selects and outputs a higher one of the voltages applied to the first memory cell and the second memory cell.

Abstract: Disclosed are devices and methods for storing values, symbols, parameters or conditions in memory devices as states, and subsequently mapping detected states as values, symbols parameters or conditions. In one implementation write operations may place first and second memory elements in a particular impedance state selected from between a low impedance or conductive state and a high impedance or insulative state. The high impedance or insulative state represents a first binary value or symbol while the low high impedance or conductive state represents a second binary value or symbol. Subsequently detected impedance states of the first and second memory elements may be mapped to the second binary value or symbol responsive to either of the detected impedance states being the high impedance or insulative state and the second detected impedance state.

Abstract: Methods for performing non-invasive thrombolysis with ultrasound using, in some embodiments, one or more ultrasound transducers to focus or place a high intensity ultrasound beam onto a blood clot (thrombus) or other vascular inclusion or occlusion (e.g., clot in the dialysis graft, deep vein thrombosis, superficial vein thrombosis, arterial embolus, bypass graft thrombosis or embolization, pulmonary embolus) which would be ablated (eroded, mechanically fractionated, liquefied, or dissolved) by ultrasound energy. The process can employ one or more mechanisms, such as of cavitational, sonochemical, mechanical fractionation, or thermal processes depending on the acoustic parameters selected. This general process, including the examples of application set forth herein, is henceforth referred to as “Thrombolysis.

Abstract: An electronic device includes one or more light sources for emitting light toward a body part of a user and one or more optical sensors for capturing light samples while each light source is turned on and for capturing dark samples while the light source(s) are turned off. A signal produced by the one or more optical sensors is demodulated produce multiple demodulated signals. Each demodulated signal is received by one or more decimation stages to produce a signal associated with each light source. Each signal associated with the light source(s) is analyzed to estimate or determine a physiological parameter of the user.

Abstract: A semiconductor memory device includes a first memory die, a control circuit, and a signal generator. The first memory die includes at least one charge pump on a memory die. The control circuit is configured to control driving of the at least one charge pump during a time period. The signal generator is configured to generate a control signal that prevents the at least one charge pump of the first memory die not to be driven at a same time with a charge pump in a second memory die different from the first memory die and to apply the generated pump enable control signal to the pump enable unit.

Abstract: A memory card is provided to include a substrate having two pairs of edges facing each other, a plurality of first row terminals that are arranged adjacent to an edge at an insertion side of the substrate and include a first voltage power terminal for applying a first voltage and a first ground terminal, a plurality of second row terminals that are spaced farther apart from the edge at the insertion side than the plurality of first row terminals and include a second voltage power terminal for applying a second voltage and first data terminals, and a plurality of third row terminals that are spaced farther apart from the edge at the insertion side than the plurality of second row terminals and include second data terminals.

Abstract: In an example, a memory device has a first string of memory cells selectively connected to a first data line, a second string of memory cells selectively connected to a second data line, and a transistor that selectively connects the first data line to the second data line, thereby permitting connecting the first and second data lines in series before programming or sensing memory cells of the first and second strings of memory cells.

Abstract: A semiconductor device according to one embodiment includes a unique ID generation circuit configured to generate a unique ID using a memory array including a plurality of complementary cells, each of the complementary cells includes first and second memory cells MC1 and MC2. The unique ID generation circuit uses, when data in the complementary cell read out in a first state in which an initial threshold voltage of the first memory cell MC1 has been virtually offset and data in the complementary cell read out in a second state in which an initial threshold voltage of the second memory cell MC2 has been virtually offset coincide with each other, the data in the complementary cell as the unique ID.