Patents Examined by Hiep T. Nguyen
  • Patent number: 11327660
    Abstract: A storage system having high reliability and IO processing performance is realized. The storage system includes: a first arithmetic unit configured to receive an input and output request and perform data input and output processing; a first memory connected to the first arithmetic unit; a plurality of storage drives configured to store data; a second arithmetic unit; and a second memory connected to the second arithmetic unit. The first arithmetic unit instructs the storage drive to read data, the storage drive reads the data and stores the data in the second memory, the second arithmetic unit stores the data stored in the second memory in the first memory, and the first arithmetic unit transmits the data stored in the first memory to a request source of a read request for the data.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 10, 2022
    Assignee: HITACHI, LTD.
    Inventors: Takashi Nagao, Yuusaku Kiyota, Hideaki Monji, Tomohiro Yoshihara
  • Patent number: 11327679
    Abstract: A method is used for bitmap-based synchronous replication in a data protection system. The method includes, upon re-establishing communication with a first storage node, requesting, by a second storage node, a first bitmap from the first storage node. The method includes determining, by the second storage node, a set of data blocks to change on the first storage node based on the first bitmap and a second bitmap on the second storage node. The method also includes sending, by the second storage node to the first storage node, the set of data blocks.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: May 10, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Tianfang Xiong, Wai Yim, Yifeng Lu, Yue Yang
  • Patent number: 11321006
    Abstract: A method of data loss prevention during transitions from a replication source, the method including: initiating a transition from using a first data repository as a source for data replication to using a second data repository as the source for data replication; prior to completing the transition and responsive to determining that one or more storage operations directed to the first data repository have not been replicated to the second data repository, delaying transition of the second data repository as the source for data replication; and responsive to completing the transition, promoting the second data repository as the source for data replication such that all storage operations received after completing the transition are directed to the second data repository.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: May 3, 2022
    Assignee: PURE STORAGE, INC.
    Inventors: David Grunwald, Thomas Gill, Connor Brooks, Larry Touchette, Saurabh Shukla
  • Patent number: 11314422
    Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 26, 2022
    Assignee: NETLIST, INC.
    Inventor: Hyun Lee
  • Patent number: 11314425
    Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system and performing error recovery for the set of CWs using a set of error handing (EH) steps until each CW of the set of CWs are indicated as correctable in the error recovery data structure. The error recovery can include determining if each CW of the set of CWs is correctable by an EH step, storing indications of CWs determined correctable by the EH step in the error recovery data structure, determining if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Harish Reddy Singidi, Ting Luo, Kishore Kumar Muchherla
  • Patent number: 11314424
    Abstract: Systems and methods for performing file-level restore operations for block-level data volumes are described. In some embodiments, the systems and methods restore data from a block-level data volume contained in secondary storage by receiving a request to restore one or more files from the block-level data volume, mounting a virtual disk to the block-level data volume, accessing one or more mount paths established by the virtual disk between the data agent and the block-level data volume, and browsing data from one or more files within the block-level data volume via the established one or more mount paths provided by the virtual disk.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 26, 2022
    Assignee: Commvault Systems, Inc.
    Inventors: Sri Karthik Bhagi, Sunil Kumar Gutta, Vijay H. Agrawal, Rahul S. Pawar
  • Patent number: 11294577
    Abstract: A non-volatile memory includes a plurality of data storage units arranged in an array, a plurality of redundant data storage units arranged in at least one row and a plurality of redundant address storage units arranged in at least one row. A storage size of each of the data storage units is word. Each of the data storage units is addressable by a row address and a column address. One of the redundant data storage units in a first column is configured to substitute for one of the data storage units in a second column. One of the redundant address storage units in a third column is configured to record the row address representative of the substituted one of the data storage units.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 5, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Hua Lu, Hsin-Pang Lu
  • Patent number: 11294592
    Abstract: A data processing method including: searching for a smallest data unit of a buffer with regard to appending data in an append write request; sequentially writing at least some of the appending data into the smallest data unit of the buffer to obtain a first smallest data unit to be stored, and writing data not yet written in the appending data into at least one smallest data unit to obtain at least one second smallest data unit to be stored; writing the first smallest data unit to be stored into a storage device in an overwriting manner, and sequentially writing the at least one second smallest data unit to be stored into the storage device; and buffering a smallest data unit not fully written that corresponds to the appending data. The present disclosure ensures data integrity, increase operation convenience, and write operation efficiency.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: April 5, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Dongzheng Wu, Chengyu Dong, Jinxin Liu
  • Patent number: 11287983
    Abstract: A RAID storage management system includes a plurality of RAID storage devices and a controller configured to manage the plurality of RAID storage devices. The RAID storage management system also includes at least one expander operatively connected to the controller and operatively connected to the plurality of RAID storage devices. The expander is configured to receive a request from the controller for a RAID operation. The expander is also configured to, upon receiving the request, operate to assist the controller in performing the requested RAID operation.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: March 29, 2022
    Assignee: Seagate Technology LLC
    Inventors: Indrajit Zagade, Vishal Thakkar, Prasad Ramchandra Kadam
  • Patent number: 11287991
    Abstract: A memory system includes a memory device and a controller. The controller includes: a first internal storage, a second internal storage configured to store a recovery code, a level detector configured to detect whether a change in levels of power supply voltages exceeds respectively reference level ranges, a protection operation component configured to determine entry into and exit from a protection mode in response to a result of the level detector, to perform a first protection operation of generating event information and a snapshot information and storing the event and snapshot information in the first internal storage, and a recovery operation component configured to receive the recovery code from the second internal storage in response to exiting from the protection mode, to enter the recovery mode, to receive the event information and the snapshot information from the first internal storage, and to perform a recovery operation on the memory device.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: March 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Jeong Hyun Yoon
  • Patent number: 11281396
    Abstract: Methods, systems, and computer storage media for providing temporary storage for data that has to be durably stored based on a replica set that includes a partial replica and a set of full replicas in a distributed computing environment. The partial replica of the replica set temporarily and durably stores data but does not persist the data when the set of full replicas have communicated a promise response to store the data. In operation, instructions to communicate promise responses are communicated to a replica set comprising a partial replica and a set of full replicas. A promise response indicates that a replica in the replica set will commit the data block of the write request. Promise responses are received from the set of full replicas. Based on receiving promise responses from the set of full replicas, a forget instruction is communicated to the partial replica to forget the data block.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: March 22, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Garret Buban
  • Patent number: 11275515
    Abstract: A memory device configured to descramble scrambled composite data. In one approach, the scrambled composite data is provided by an XOR (exclusive OR operation) of more than one data set scrambled with non-linear scramblers. A memory device is configured to receive scramble codes generated by non-linear scramblers and perform an XOR of the scrambled composite data with the scramble codes to remove scrambling from the composite data. In one example, the scrambled data sets are data to be written to a NAND device at more than one bit per cell density (e.g., MLC, TLC, QLC, PLC, etc.). For example, the scrambled data sets may be written to the NAND device in more than one programming pass. In one example, the scrambled composite data is used to read the scrambled data sets that have been written in a first programming pass.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Patrick Robert Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak
  • Patent number: 11262932
    Abstract: Described is a system for discovering and configuring backup settings for protectable storage assets of a storage array. The system may perform such discovery and configuration for a storage array by providing an efficient centralized management capability. In addition, the centralized management capability allows for the creation of backup policies that are host-aware. Accordingly, the system may account for the interrelationship between storage devices, storage groups, and host devices to prevent potential inconsistencies and conflicts that may arise when creating a centralized backup policy.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 1, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Shivam Chaturvedi, LahariCharan Bejjanke, Sanjeev Lochab, Pawan Singh, Rintu Kanp, Upanshu Singhal
  • Patent number: 11249674
    Abstract: Systems, apparatus and methods are provided for electrical mirroring implemented by a storage controller in a non-volatile storage system. In one embodiment, a non-volatile storage system may comprise a plurality of non-volatile storage devices and a storage controller. The storage controller may be configured to perform an electrical mirroring configuration process comprising: determining a system topology of the non-volatile storage system and which targets are in mirrored non-volatile storage devices and setting respective register bits in the storage controller for all targets in all mirrored non-volatile storage devices of the plurality of non-volatile storage devices.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: February 15, 2022
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Gang Zhao, Jie Chen, Lin Chen, Wei Jiang
  • Patent number: 11243697
    Abstract: Technology for choosing a design for a computer data storage system having a prescribed reliability. The selection of a “matching storage system,” matching the prescribed reliability is based on computation of first and second reliability indicators.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: February 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Praveen Viraraghavan, Ilias Iliadis, Mark Alfred Lantz
  • Patent number: 11231884
    Abstract: A system includes logic stored in the memory and executable by the processor to cause the processor to obtain the set of primary data objects and the set of residual data objects, each residual data object of the set of residual data objects being associated with, and representative of rounding that led to, a respective primary data object of the set of primary data objects, to evaluate, for each residual data object of the set of residual data objects, whether removal of the residual data object breaches a data integrity rule, to cause the processor to, for each residual data object of the set of residual data objects for which the removal breaches the data integrity rule, implement an optimization to attempt to identify at least one adjustment to the set of primary data objects, the set of residual data objects, or both the set of primary data objects and the set of residual data objects, that allows the removal to proceed without breaching the data integrity rule, to remove, from the set of residual data o
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 25, 2022
    Assignee: Chicago Mercantile Exchange Inc.
    Inventor: Carl Erik Thornberg
  • Patent number: 11226920
    Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: January 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: James Brian Johnson, Brent Keeth
  • Patent number: 11221801
    Abstract: A data writing method and a storage controller are provided. The data writing method includes: selecting a plurality of first dies and a plurality of second dies from a plurality of dies of the flash memory module, receiving a writing command and determining an amount of write data corresponding to the writing command, and when the amount of write data is greater than a threshold, writing in a pSLC mode the write data into the second dies.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: January 11, 2022
    Assignee: Acer Incorporated
    Inventors: Guan-Yu Hou, Tz-Yu Fu
  • Patent number: 11216205
    Abstract: A checkpoint server for containers is disclosed. The checkpoint server generates checkpoint images of running containers or of warmed-up containers. These checkpoint images are restored such that the order in which memory pages are accessed can be recorded or logged. During a restore operation to a host, the memory pages are transmitted in accordance with the page order log. The container can then begin serving requests before all of the memory pages have been transmitted to the host.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: January 4, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Victor Fong, Kenneth Durazzo
  • Patent number: 11216386
    Abstract: Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Vivek Kozhikkottu, Suresh Chittor, Esha Choukse, Shankar Ganesh Ramasubramanian