Patents Examined by Hiep T. Nguyen
  • Patent number: 10776024
    Abstract: A method for accessing data by a solid state disk is provided, which includes steps of: configuring at least one NAND die to be dedicated for writing random data and other NAND dies to be dedicated for writing sequential data; configuring one of the NAND dies dedicated for writing the sequential data to include memory cells each of which is allowed to be used for storing a data stream having the maximum number of bits; configuring one of the NAND dies dedicated for writing the random data to include memory cells each of which is used for storing a data stream having the number of bits that is smaller the maximum number of the bits; and determining the total number of the bits of one of the data streams of the random data written by the NAND dies and accordingly reconfiguring the NAND dies.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: September 15, 2020
    Assignee: ADATA TECHNOLOGY CO., LTD.
    Inventor: Kuo-Hua Yuan
  • Patent number: 10761749
    Abstract: First and second vectors each respectively having first and second magnitudes and first and second phase angles relative to a reference axis are determined by a processing device based on a set of error values corresponding a current processing level for processing data in memory operations on memory cells of a memory component. An estimated processing level offset is generated based on a comparison between at least one of a difference between the first magnitude and the second magnitude or a difference between the first phase angle and the second phase angle. An updated processing level is generated based on the estimated processing level offset, and the updated processing level replaces the current processing level.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Larry J. Koudele
  • Patent number: 10761777
    Abstract: A Data Storage Device (DSD) includes a first memory for storing data and a Storage Class Memory (SCM) for storing data. The SCM has at least one characteristic of being faster than the first memory in storing data, using less power to store data than the first memory, and providing a greater usable life than the first memory for repeatedly storing data in a same memory location. At least a portion of the SCM is allocated or reserved for use by a host, and logical addresses assigned to the SCM are mapped to device addresses of the first memory identifying locations for storing data in the first memory. The host is provided with an indication of the logical addresses assigned to the SCM to allow the host to retrieve data from and store data in the DSD or to directly access data using the logical addresses assigned to the SCM.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 1, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: James N. Malina, Albert H. Chen, Takeaki Kato
  • Patent number: 10761738
    Abstract: A RAID storage management system includes a plurality of RAID storage devices and a controller configured to manage the plurality of RAID storage devices. The RAID storage management system also includes at least one expander operatively connected to the controller and operatively connected to the plurality of RAID storage devices. The expander is configured to receive a request from the controller for a RAID operation. The expander is also configured to, upon receiving the request, operate to assist the controller in performing the requested RAID operation.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: September 1, 2020
    Assignee: Seagate Technology LLC
    Inventors: Indrajit Zagade, Vishal Thakkar, Prasad Ramchandra Kadam
  • Patent number: 10761843
    Abstract: An information processing device includes a first package including a first arithmetic circuit, first cache memory and a transmitting circuit, as well as a second package including a second arithmetic circuit, second cache memory and a receiving circuit. The first arithmetic circuit is configured to provide transfer data to the first cache memory that is destined for the second cache memory. The transmitting circuit is configured to transmit to the receiving circuit an indication of a data transfer of the transfer data and to restrict use of the first cache memory for data other than the transfer data during the data transfer. The receiving circuit is configured to receive the indication of the data transfer, to acquire the transfer data stored in the first cache memory and to store the acquired transfer data in the second cache memory.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: September 1, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Shimizu, Yasuhiro Watanabe
  • Patent number: 10761730
    Abstract: One aspect of the present disclosure provides a method for configuring a disk array of an electronic device. The method includes: storing configuration information of the disk array; acquiring the stored configuration information if the electronic device is turned on; and configuring the disk array according to the configuration information.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: September 1, 2020
    Assignee: LENOVO (BEIJING) CO., LTD.
    Inventor: Kehong Du
  • Patent number: 10747703
    Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: August 18, 2020
    Assignee: Rambus Inc.
    Inventors: Liji Gopalakrishnan, Ian Shaeffer, Yi Lu
  • Patent number: 10747454
    Abstract: Apparatus, media, methods, and systems for data storage systems and methods for self-adaptive chip-enable setup time. A data storage system may comprise one or more non-volatile memory device and a controller. The controller is configured to determine whether a command to a first non-volatile memory device of the one or more non-volatile memory devices is dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, update a first counter value indicating a number of commands to the first non-volatile memory device that are dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, increase a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time duration, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: August 18, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niang-Chu Chen, Jun Tao
  • Patent number: 10747450
    Abstract: A system includes at least one memory device, at least one processor in communication with the at least one memory device, a guest operating system (OS) associated with a device driver, and an out-of-memory (OOM) handler executing on the at least one processor. The OOM handler is configured to locate a memory device of the at least one memory device, send an out-of-memory request to the device driver that is associated with the memory device, and receive a response from the memory device. The device driver is configured to query an amount of unusable device memory, request to plug the unusable device memory, and report the previously unusable device memory as now usable memory.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 18, 2020
    Assignee: Red Hat, Inc.
    Inventors: David Hildenbrand, Luiz Capitulino
  • Patent number: 10740001
    Abstract: Embodiments of the present disclosure provide a method, an apparatus and a computer program product for managing an input/output (I/O). The method comprises, in response to receiving a first I/O request of a first type for a storage device, determining whether there exists at least one credit available to the first type of I/O requests. Each of the at least one credit indicates I/O processing capability reserved by the storage device for the first type of I/O requests. The method further comprises allocating a first credit to the first I/O request based on a result of the determining. The method further comprises performing, by using the first credit, an I/O operation requested by the first I/O request on the storage device. Moreover, the method further comprises, in response to completion of the I/O operation, recycling the first credit for use by a subsequent I/O request. Embodiments of the present disclosure can implement dynamic allocation of I/O processing capability for different types of I/Os.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 11, 2020
    Assignee: Dell Products L.P.
    Inventors: Lifeng Yang, Xinlei Xu, Liam Li, Ruiyong Jia, Yousheng Liu
  • Patent number: 10732861
    Abstract: Embodiments of the present disclosure relate to facilitating efficient access to electronic content via an intermediate caching layer between a client device and remote storage system. In particular, systems and methods disclosed herein generate and maintain a regional cache on a data center that includes a subset of digital content items from a collection of digital content items stored on the remote storage system. For example, in response to receiving a data request, the systems and methods disclosed herein determine whether a digital content item corresponding to the data request exists on an intermediate caching layer including both a local data center and one or more remote data centers. The systems and methods facilitate obtaining copies of requested digital content items from the regional caches when available, resulting in faster responses to data requests while decreasing a number of times a client directly accesses the remote storage system.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 4, 2020
    Assignee: QUALTRICS, LLC
    Inventors: Matthew Brasfield, Christopher Kuchin, David Mecham, Jared Ririe
  • Patent number: 10732882
    Abstract: The present invention provides a temporary memory processing method including: receiving a write command including a write data and a write address; determining whether a corresponding temporary address is in a missed state to generate a determined result; and determining whether to write the write data into a corresponding buffer address of a buffer memory according to the determined result.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: August 4, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Yen-Ju Lu
  • Patent number: 10725923
    Abstract: An apparatus comprises a cache memory to store data as a plurality of cache lines each having a data size and an associated physical address in a memory, access circuitry to access the data stored in the cache memory, detection circuitry to detect, for at least a set of sub-units of the cache lines stored in the cache memory, whether a number of accesses by the access circuitry to a given sub-unit exceeds a predetermined threshold, in which each sub-unit has a data size that is smaller than the data size of a cache line, prediction circuitry to generate a prediction, for a given region of a plurality of regions of physical address space, of whether data stored in that region comprises streaming data in which each of one or more portions of the given cache line is predicted to be subject to a maximum of one read operation or multiple access data in which each of the one or more portions of the given cache line is predicted to be subject to more than one read operation, the prediction circuitry being configured
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: July 28, 2020
    Assignee: Arm Limited
    Inventors: Lei Ma, Alexander Alfred Hornung, Ian Michael Caulfield
  • Patent number: 10719246
    Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: July 21, 2020
    Assignee: Netlist, Inc.
    Inventor: Hyun Lee
  • Patent number: 10698816
    Abstract: Various examples are directed to a host device comprising a memory system, a host device memory, and a processor. The processor is programmed to receive from the memory system a first logical-to-physical (L2P) pointer message that comprises a first L2P pointer and a first digital signature. The processor executes a cryptographic operation based at least in part on the first L2P pointer and a cryptographic key and verifies the first digital signature based at least in part on the cryptographic operation. The processor caches the first L2P pointer at the host device memory.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Zoltan Szubbocsev, Alberto Troia, Federico Tiziani, Antonino Mondello
  • Patent number: 10691339
    Abstract: A method, non-transitory computer readable medium, and device that assists with reducing initialization duration and performance impact during configuration of storage drives includes identifying a plurality of new storage drives in a storage system. Next, one or more zeroed out storage drives is identified from the identified plurality of new storage drives based on information present in a data portion of each the identified plurality of new storage drives. A volume group comprising the identified one or more zeroed out drives is created and this created volume group is provided for data operation.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: June 23, 2020
    Assignee: NETAPP, INC.
    Inventors: Mahmoud K. Jibbe, Charles Binford
  • Patent number: 10691550
    Abstract: A storage control apparatus includes a memory configured to store meta-information for associating addresses of a logical area and a physical area with each other, and a processor coupled to the memory and configured to read out first meta-information corresponding to a first logical area from the memory, specify a first address of the physical area corresponding to a copy source address of the data based on the first meta-information, read out second meta-information corresponding to a second logical area that is set as a copy destination of the data in the logical area from the memory, specify a second address of the physical area corresponding to a copy destination address of the data based on the second meta-information, and execute copy of the data by associating the first address and the second address with each other as storage areas of the data.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: June 23, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yoshinari Shinozaki, Takeshi Watanabe, Norihide Kubota, Yoshihito Konta, Toshio Kikuchi, Naohiro Takeda, Yusuke Kurasawa, Yuji Tanaka, Marino Kajiyama, Yusuke Suzuki
  • Patent number: 10678702
    Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: June 9, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Sergey Blagodurov, Andrew G. Kegel
  • Patent number: 10678685
    Abstract: A memory management method applicable to a data storage device is provided. The memory management method includes steps of: requesting a private memory space from a host; recording a reserved memory space given by the host; dividing a mapping table into a plurality of sub-mapping tables; determining whether a capacity of the reserved memory space is sufficient to store the sub-mapping tables; and if yes, uploading the sub-mapping tables to the reserved memory space via an interface logic.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: June 9, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Hong-Jung Hsu, Huang-Hsing Wu
  • Patent number: 10678440
    Abstract: I/O storage processing behavior is controlled on a storage system based on an application instance of an I/O request. I/O storage processing behavior may be associated with application instances on a host by creating a table or other data structure that assigns identifiers to each application instance and specifies associate behavior(s) with the application instance. The table may associate behavior to application instances based on logical groupings of application instances, which may be based on existing defined groups or other logical entities, for example, a container or VM. A host may communicate the table to a storage system, and the storage system may store information from the table. An I/O request on the host may be tagged with an ID from the table, and sent to the storage system, which controls the I/O storage processing of the I/O request according to the tagged ID.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 9, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Kurumurthy Gokam, Arieh Don, Gopinath Marappan