Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter transacts a streak for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter. Following the minimum burst length, the arbiter decides to start a new streak of commands of a different type based on a first set of one or more conditions indicating intra-burst efficiency.

Abstract: A method of allocating a memory for driving a neural network including obtaining first capacity information of a space to store an input feature map of a first layer from among the layers of the neural network, and second capacity information of a space to store an output feature map of the first layer, and allocating a first storage space to store the input feature map in the memory based on an initial address value of the memory and the first capacity information and a second storage space to store the output feature map in the memory based on a last address value of the memory and the second capacity information.

Abstract: In a particular embodiment, a dataset that is synchronously replicated across a plurality of storage systems is stored on a particular storage system. The storage system identifies input/output (I/O) requests directed to the dataset. The one or more I/O requests are initiated by an application hosted on a platform of the first storage system. The storage system services the one or more I/O requests directed to the dataset.

Abstract: Embodiments of the present disclosure relate to autonomous data protection. An input/output (I/O) stream can be received for a storage device. One or more anomalies corresponding to the I/O stream can be identified. At least one of the one or more anomalies can be offloaded anomalies to a remote storage based on a capacity of memory allocated to store at least one snapshot of the storage device that include at least one of the one or more anomalies.

Abstract: Compact representation for input workloads is generated in a memory system, A memory controller includes firmware (FW) and an encoder including recurrent encoding blocks. Each recurrent encoding block receives one of input commands in an input workload, and generates a hidden state vector corresponding to the received input command by applying a set of activation functions on the received input command. The last encoding block generates a final hidden state vector as a compact representation vector corresponding to the input commands. The firmware determines a distance function between the compact representation vector and each of multiple compact workload vectors and tunes at least one of firmware parameters based on the determined distances.

Abstract: Transitioning between replication sources for data replication operations, including: delaying a transition from using a first data repository as a source for data replication to using a second data repository as the source for data replication after detecting that one or more storage operations directed to the first data repository have not been replicated to the second data repository; and promoting the second data repository as the source for data replication such that storage operations received after completing the transition are directed to the second data repository.

Abstract: A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.

Abstract: A data processing apparatus and a vehicle having the same are provided. A data processing apparatus of a vehicle includes: a first memory having a plurality of storage areas to which each address of a plurality of addresses is allocated; and a processor configured to confirm information of data received from a first device, confirm an address corresponding to the received data based on the confirmed information of data, and store the received data in a storage area of the plurality of storage areas corresponding to the confirmed address.

Abstract: Systems, apparatuses, and methods related to multiple artificial neural networks (ANNs) in memory. Such ANNs can be implemented within a memory system (including a number of memory devices) at different granularities. For example, multiple ANNs can be implemented within a single memory device and/or a single ANN can be implemented over multiple memory devices (such that multiple memory devices are configured as a single ANN). The memory system having multiple ANNs can operate each ANN independently from each other such that multiple ANN operations can be concurrently performed.

Abstract: In an approach a request to write data to memory is received, wherein the memory includes: a first set of dynamic random-access memory (DRAM) accessible via a first memory channel, and a first set of storage class (SCM) memory accessible via a second memory channel. The data is written to the first set of DRAM via the first memory channel. The data is mirrored to the first set of SCM via the second memory channel.

Abstract: A method for authorizing I/O (input/output) commands in a storage cluster is provided. The method includes generating a token responsive to an authority initiating an I/O command, wherein the token is specific to assignment of the authority and a storage node of the storage cluster. The method includes verifying the I/O command using the token, wherein the token includes a signature confirming validity of the token and wherein the token is revocable.

Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.

Abstract: Memory devices, systems and methods are described, such as those including a dynamically configurable channel depth. Devices, systems and methods are described that adjust channel depth based on hardware and/or software requirements. One such device provides for virtual memory operations where a channel depth is adjusted for the same physical memory region responsive to requirements of different memory processes.

Abstract: Devices, systems and methods for improving the performance of a memory device are described. An example method includes performing, based on a plurality of read voltages, read operations on each of a plurality of pages of a memory device, determining, based on the read operations for each page of the plurality of pages, a ones count in each page and a checksum of an error correcting code for each page, generating a first estimator for the checksum and a second estimator for the ones count based on a polynomial regression, determining, based on the first estimator and the second estimator, an updated plurality of read voltages, and applying the updated plurality of read voltages to the memory device to retrieve information from the memory device.

Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for operating a cache drive in a data storage system. The methods include receiving, from an IO interface in the cache drive of the compute server, a write request to write data; caching the data corresponding to the write request in a cache storage of the cache drive of the compute server; performing one or more compute processes on the data; and in response to performing the one or more compute processes on the data, providing the processed data to a storage cluster for storing via the IO interface that is communicatively coupled to the storage cluster.

Abstract: Methods and systems for a networked storage system are provided. One method includes: receiving, by a first storage node, a request to modify data stored using a logical storage object presented by the first storage node, the first storage node communicating with a second storage node configured as a failover partner of the first storage node; transmitting, by the first storage node, an invalidation request to the second storage node to invalidate an entry in a storage location cache of the second storage node, the entry indicating a storage location where data is stored by the first storage node, before modification; and responding, by the first storage node, to the request after modifying the data and upon receiving a response from the second storage node indicating successful invalidation of the entry.

Abstract: The present disclosure generally relates to efficiently relocating data within a data storage device. By implementing an error correction code (ECC) module in a complementary metal oxide semiconductor (CMOS) chip for each memory die within a memory array of a memory device, the data can be relocated more efficiently. The ECC decodes the codewords at the memory die. The metadata is then extracted from the decoded codewords and transferred to a controller of the data storage device. A flash translation layer (FTL) module at the controller then checks whether the data is valid by comparing the received metadata to FTL tables. If the metadata indicates the data is valid, then the data is relocated.

Abstract: Creating a replica of a storage system, including: receiving, by a first storage system from a computing device, data to be stored on the first storage system; reducing, by the first storage system, the data using one or more data reduction techniques; sending, from the first storage system to the second storage system, the reduced data, wherein the reduced data is encrypted; and sending, from the second storage system to a third storage system, the reduced data, wherein the reduced data is encrypted.

Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.

Abstract: A method that includes writing a plurality of codewords to a plurality of memory blocks of a memory device, where each of the plurality of codewords has a physical codeword index corresponding to a respective memory block in which each codeword is written, and assigning a virtual codeword index to each of the plurality of codewords to provide a plurality of virtual codeword indices, where assigning the virtual codeword index to each of the plurality of codewords is based, at least in part, on a location in a virtual block among a plurality of virtual blocks of memory cells corresponding to the physical codeword index of each codeword among the plurality of codewords.