Patents Examined by Hiep T. Nguyen
  • Patent number: 10719246
    Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: July 21, 2020
    Assignee: Netlist, Inc.
    Inventor: Hyun Lee
  • Patent number: 10698816
    Abstract: Various examples are directed to a host device comprising a memory system, a host device memory, and a processor. The processor is programmed to receive from the memory system a first logical-to-physical (L2P) pointer message that comprises a first L2P pointer and a first digital signature. The processor executes a cryptographic operation based at least in part on the first L2P pointer and a cryptographic key and verifies the first digital signature based at least in part on the cryptographic operation. The processor caches the first L2P pointer at the host device memory.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Zoltan Szubbocsev, Alberto Troia, Federico Tiziani, Antonino Mondello
  • Patent number: 10691550
    Abstract: A storage control apparatus includes a memory configured to store meta-information for associating addresses of a logical area and a physical area with each other, and a processor coupled to the memory and configured to read out first meta-information corresponding to a first logical area from the memory, specify a first address of the physical area corresponding to a copy source address of the data based on the first meta-information, read out second meta-information corresponding to a second logical area that is set as a copy destination of the data in the logical area from the memory, specify a second address of the physical area corresponding to a copy destination address of the data based on the second meta-information, and execute copy of the data by associating the first address and the second address with each other as storage areas of the data.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: June 23, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yoshinari Shinozaki, Takeshi Watanabe, Norihide Kubota, Yoshihito Konta, Toshio Kikuchi, Naohiro Takeda, Yusuke Kurasawa, Yuji Tanaka, Marino Kajiyama, Yusuke Suzuki
  • Patent number: 10691339
    Abstract: A method, non-transitory computer readable medium, and device that assists with reducing initialization duration and performance impact during configuration of storage drives includes identifying a plurality of new storage drives in a storage system. Next, one or more zeroed out storage drives is identified from the identified plurality of new storage drives based on information present in a data portion of each the identified plurality of new storage drives. A volume group comprising the identified one or more zeroed out drives is created and this created volume group is provided for data operation.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: June 23, 2020
    Assignee: NETAPP, INC.
    Inventors: Mahmoud K. Jibbe, Charles Binford
  • Patent number: 10678685
    Abstract: A memory management method applicable to a data storage device is provided. The memory management method includes steps of: requesting a private memory space from a host; recording a reserved memory space given by the host; dividing a mapping table into a plurality of sub-mapping tables; determining whether a capacity of the reserved memory space is sufficient to store the sub-mapping tables; and if yes, uploading the sub-mapping tables to the reserved memory space via an interface logic.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: June 9, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Hong-Jung Hsu, Huang-Hsing Wu
  • Patent number: 10678440
    Abstract: I/O storage processing behavior is controlled on a storage system based on an application instance of an I/O request. I/O storage processing behavior may be associated with application instances on a host by creating a table or other data structure that assigns identifiers to each application instance and specifies associate behavior(s) with the application instance. The table may associate behavior to application instances based on logical groupings of application instances, which may be based on existing defined groups or other logical entities, for example, a container or VM. A host may communicate the table to a storage system, and the storage system may store information from the table. An I/O request on the host may be tagged with an ID from the table, and sent to the storage system, which controls the I/O storage processing of the I/O request according to the tagged ID.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 9, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Kurumurthy Gokam, Arieh Don, Gopinath Marappan
  • Patent number: 10678702
    Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: June 9, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Sergey Blagodurov, Andrew G. Kegel
  • Patent number: 10649695
    Abstract: A command processing method and a storage controller are provided. The command processing method includes: receiving multiple read-modify-write (RMW) commands by a command processing pool of the storage controller, wherein each of the RMW commands includes a read command and a write command in pairs; locking a queue by the command processing pool and transmitting a pending first read command of the RMW commands in the command processing pool to the queue; when a second read command paired with a second write command of the RMW commands is pending, not locking the queue by the command processing pool and not transmitting the second write command to the queue; and when a third read command paired with a third write command of the RMW commands is not pending, locking the queue by the command processing pool and transmitting the third write command to the queue.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: May 12, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventor: Shih-Tien Liao
  • Patent number: 10635547
    Abstract: Systems for multi-cluster virtualized computing system management. A method for performing virtual entity replication between source computing clusters and target computing clusters commences upon establishing a virtual entity naming convention that is observed by both the source computing clusters and the target computing clusters. A snapshot from a source cluster is associated with a global snapshot ID before being transmitted to a target computing cluster. At some point in time, the source cluster will initiate acts to replicate a virtual entity to a particular data state that is associated with a particular named snapshot. A second replication protocol then commences. The second replication protocol includes exchanges that serve to determine whether or not the target computing cluster has a copy of a particular named snapshot as named by the global snapshot ID, and if so, to then initiate virtual entity replication at the target computing cluster using the named snapshot.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 28, 2020
    Assignee: Nutanix, Inc.
    Inventors: Praveen Kumar Padia, Bharat Kumar Beedu, Kiran Tatiparthi, Krishnaveni Budati, Wangzi He
  • Patent number: 10635346
    Abstract: The present disclosure describes technologies and techniques for use with a data storage controller (such as a non-volatile memory (NVM) controller) to implement self-trimming of media data. In illustrative examples, an NVM controller stores a stream of video data in a NAND storage device, such as video obtained by a security camera. The controller also stores time stamps corresponding to portions of the video data. The controller then periodically (or during idle times) scans the stored information to identify video data that has exceeded a maximum data lifetime, such as data older than one week. Such data is deemed to be old/expired and is trimmed by the controller (by, e.g., marking corresponding entries in an allocation table as deleted or invalid). In this manner, the controller performs self-trimming of older video data to, for example, limit write amplification. NVMe examples are provided.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 28, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Avichay Haim Hodes, Guy Freikorn
  • Patent number: 10628051
    Abstract: A data storage device includes a data storage medium and a controller. The controller performs a boot-up sequence that includes operations that transition the data storage device from a lower operational state to a higher operational state in which the data storage device is ready to service host commands. The controller also carries out metadata updating operations independently of the boot-up sequence operations. Carrying out the metadata updating operations independently of the boot up sequence operations prevents the metadata updating operations from substantially contributing to a boot-up time.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: April 21, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jian Qiang, Tan Choon Kiat, Shen Jin Quan, Chng Yong Peng
  • Patent number: 10615824
    Abstract: Symbols are loaded into a diagonal anti-diagonal structure. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol are positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Tobias Blaettler, Charles J. Camp, Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis
  • Patent number: 10613758
    Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include: a semiconductor memory device to which an address mapping table including a plurality of map segments is stored; and a controller configured to load and store, during a read operation, one or more map segments selected from among the plurality of map segments. The controller may include: a compression engine configured to compress the one or more map segments and generate one or more compressed map segments and metadata corresponding thereto; a map data loading buffer configured to store the one or more compressed map segments and the metadata; and a processor configured to store the one or more compressed map segments to a random access memory (RAM) using the metadata.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: April 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Young Ick Cho, Byeong Gyu Park
  • Patent number: 10606518
    Abstract: A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a retry table. In addition, plural retry read-voltage sets are recorded in the retry table, and the retry table is divided into plural retry sub-tables. The plural retry read-voltage sets are classified into plural groups. The plural retry read-voltage sets are recorded into the corresponding retry sub-tables. The non-volatile memory is connected with the control circuit. During a read retry process of a read cycle, the control circuit performs a hard decoding process according to a retry sub-table of the plural retry sub-tables. If the hard decoding process fails, the control circuit performs a soft decoding process according to another retry sub-table of the plural retry sub-tables.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: March 31, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Hsiao-Chang Yen
  • Patent number: 10606519
    Abstract: A storage system includes a storage controller that is configured to receive an input-output (IO) request and to obtain a flow control window size of the storage system. The flow control window size is dynamically adjustable by the storage controller based at least in part on an IO latency of the storage system. The storage controller is configured, in response to determining that an actual size of a portion of the IO request to be processed is greater than the flow control window size, to add an entry corresponding to the portion of the IO request to a flow control queue of the storage system with an indication that the portion of the IO request has an effective size equal to the flow control window size. The storage controller is further configured to process the entry in the flow control queue corresponding to the portion of the IO request using the actual size of the portion of the IO request.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: March 31, 2020
    Assignee: EMC IP Holding Company LLC
    Inventor: Vladimir Shveidel
  • Patent number: 10593382
    Abstract: A memory device performs first training including a plurality of loop operations to align a main clock signal and a data clock signal, which are received from a memory controller. A method of operating the memory device includes generating division ratio information indicating a division ratio set based on a frequency ratio of the main clock signal to the data clock signal and transmitting the division ratio information to the memory controller to perform the first training.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Seok Kang, Byung-Chul Kim
  • Patent number: 10592419
    Abstract: A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; and a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: March 17, 2020
    Assignee: SK hynix Inc.
    Inventors: Yong-Woo Lee, Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Jae-Jin Lee, Hun-Sam Jung
  • Patent number: 10579301
    Abstract: A processing platform is configured to communicate over a network with one or more client devices, and to receive a request from a given one of the client devices for a proposed configuration of a storage system. The processing platform identifies based at least in part on the received request at least one processor to be utilized in implementing the storage system, selects a particular one of a plurality of storage system performance models based at least in part on the identified processor, computes a performance metric for the storage system utilizing the selected storage system performance model and one or more characteristics of the identified processor, generates presentation output comprising: (i) the performance metric, and (ii) information characterizing at least a portion of the proposed configuration of the storage system, and delivers the presentation output to the given client device over the network.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 3, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Dan Aharoni, Rui Ding, Mingjie Zhou
  • Patent number: 10579578
    Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: James Brian Johnson, Brent Keeth
  • Patent number: 10579535
    Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Lihu Rappoport, Jared Warner Stark, IV, Franck Sala, Michael Tal, Gil Shmueli, Adrian Flesler