Abstract: A memory device includes: a memory cell array; a data selector configured to receive data from the memory cell array, and to output the received data as first sub-data and second sub-data; a cyclic redundancy check (CRC) generator configured to generate first CRC values corresponding to the first sub-data, and to generate second CRC values corresponding to the second sub-data; a CRC selector configured to determine an order of the first CRC values and the second CRC values, and to output one of the first CRC values and one of the second CRC values according to the determined order; and a transmitter configured to receive the first CRC values and the second CRC values according to the determined order, and to transmit CRC values of the data by a multilevel signaling method.

Abstract: Data protection operations including recovery operations are disclosed. A recovery operation is performed by downloading the backup to be recovered from multiple identical copies of the backup. Based on factors such as throughput, an optimal amount of data can be downloaded from each of the multiple copies. The portions downloaded from the multiple copies are rebuild or reassembled once downloaded. The assembled backup is then presented to a target for recovery.

Abstract: A system in having M memory controllers between a first memory and a second memory having N operative memory slices, where N and M are not evenly divisible, includes logic to operate the M memory controllers to linearly distribute addresses of the second memory across the N operative memory slices. The system may be utilized in commercial applications such as data centers, autonomous vehicles, and machine learning.

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Abstract: Example implementations described herein are directed to systems and methods for facilitating remote copy pair volume with data consistency. For a command received for one of a first volume and a second volume during execution of a pair synchronization process between the first volume and the second volume, example implementations can involve determining whether an address range of one of the first volume and the second volume configured to be provided to a host computer is to be locked based on the command; locking the address range of the one of the first volume and the second volume for the determination indicative of the address range of one of the first volume and the second volume is to be locked; and executing the command on the first volume and the second volume while the address range configured to be provided to the host computer is locked.

Abstract: A storage device having an improved operation speed includes memory blocks and a sudden power-off manager. The memory blocks connected to word lines as part of a super block. The sudden power-off manager in communication with the memory blocks and configured to, in response to a sudden power off, 1) select reference word lines among the word lines to group the word lines into word line zones defined using the reference word lines, 2) perform read operations on pages connected to the reference word lines to determine states of the pages connected to the reference word lines, 3) select a first erase page search zone among the word line zones based on results of the read operations, and 4) determine a first erase page located at a boundary between a program page and an erase page in the first erase page search zone.

Abstract: Various embodiments described herein provide for extending a size of a memory unit of a memory device, such as a codeword of a page of the memory device, where the memory device can be included by a memory system. In particular, some embodiments implement extending (e.g., increasing) the size of a memory unit (e.g., codeword) to store more data, such as more host data (e.g., user data) and protection data (e.g., parity data), within the memory unit while using a memory unit storage slot (e.g., codeword storage slot in a page) that is smaller in size than the extended memory unit.

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Abstract: Methods, systems, and devices for multi-purpose signaling for a memory system are described. One or more signal paths of between a host device and a memory device may be configured to support shared pathways between multiple channels and to support multiple functions. For example, a signal path may be configured to communicate a state signal for an initialization sequence of the memory device, an error signal for the memory device to indicate that errors have occurred, or a low-power signal for the host device to request that the memory device enter a low-power mode, or a combination thereof. The signal path may be shared between two or more channels of the memory device.

Abstract: A method for execution by a computing device of a storage network includes determining an encoded data slice reduction scheme for a set of encoded data slices stored in a set of storage units of the storage network, where a data segment of data is encoded into the set of encoded data slices in accordance with encoding parameters, and where the encoding parameters include a pillar width number and a decode threshold number. The method further includes maintaining storage of the set of encoded data slices in accordance with the encoded data slice reduction scheme, where the maintaining storage includes keeping, until a deletion time for the set of encoded data slices, a number of encoded data slices of the set of encoded data slices equal to or greater than the decode threshold number and less than the pillar width number.

Abstract: A method includes providing, via a command, a request of enablement of a media management operation to a memory sub-system. The method further includes providing, via the command, an indication of one of a plurality of write types to the media management operation to the memory sub-system. The media management operation can be performed using the indicated write type in response to receipt of the command.

Abstract: A system for providing data protection services for data generated by host components hosted by hosts includes persistent storage for storing data and a local data protection manager. The local data protection manager identifies a data protection trigger event associated with a host component hosted by the host, identifies an add-on library associated with the host component, identifies a data protection agent associated with the host component, and initiates performance of data protection services by the data protection agent using the add-on library.

Abstract: A data storage array is configured for m-way resiliency across a first plurality of storage nodes. The m-way resiliency causes the data storage array to direct each top-level write to at least m storage nodes within the first plurality, for committing data to a corresponding capacity region allocated on each storage node to which each write operation is directed. Based on the data storage array being configured for m-way resiliency, an extra-resilient cache is allocated across a second plurality of storage nodes comprising at least s storage nodes (where s>m), including allocating a corresponding cache region on each of the second plurality for use by the extra-resilient cache. Based on determining that a particular top-level write has not been acknowledged by at least n of the first plurality of storage nodes (where n m), the particular top-level write is redirected to the extra-resilient cache.

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.

Abstract: The disclosed technology generally describes a preliminary (e.g., triple mirroring) data protection scheme that operates by writing data as redundant (e.g., three) composite copies made up of copies of data fragments to different nodes of a data storage system. The data fragments are distributed such that any two nodes can fail yet a complete set of data remains among the remaining data fragments. Later, erasure encoding creates redundant coding fragments that are written to the nodes of a data storage system in a distributed manner along with one copy of the data fragments, such that any two nodes can fail but the complete data can still be recovered. Redundant data fragments are then deleted.

Abstract: Systems and methods facilitating separation of dataset creation from movement in file replication are described herein. A method as described herein can include scheduling, by a first system operatively coupled to a processor, a first transfer of a dataset to a second system at a first time according to a first replication schedule; scheduling, by the first system, a second transfer of the dataset to a third system at the first time according to a second replication schedule; creating, by the first system, a snapshot of the dataset at a second time that is distinct from the first time according to a snapshot schedule that is distinct from the first replication schedule and the second replication schedule; and transferring, by the first system, at least a portion of the snapshot to the second system and the third system at the first time.

Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.

Abstract: Various examples are directed to a host device comprising a memory system, a host device memory, and a processor. The processor is programmed to receive from the memory system a first logical-to-physical (L2P) pointer message that comprises a first L2P pointer and a first digital signature. The processor executes a cryptographic operation based at least in part on the first L2P pointer and a cryptographic key and verifies the first digital signature based at least in part on the cryptographic operation. The processor caches the first L2P pointer at the host device memory.

Abstract: A memory quality engine can improve the operation of a memory system by setting more effective operating parameters, disabling or removing memory devices unable to meet performance requirements, and providing evaluations between memory populations. These improvements can be accomplished by converting quality measurements of a memory population into CDF-based data, formulating comparisons of the CDF-based data to metrics for quality analysis, and applying the quality analysis. In some implementations, the metrics for quality analysis can use one or more thresholds, such as a system health threshold. Formulating the comparison to these metrics can include determining an area between a baseline frequency and a curve specified by the CDF-based data. In some implementations, this area can further be defined by a lowest frequency bound and/or can be compared as a ratio to an area of a rectangle that contains the CDF curve.