Patents Examined by Hiep T. Nguyen
  • Patent number: 10338836
    Abstract: A page aligning method for a data storage device is provided. The data storage device includes a non-volatile memory and the page aligning method includes steps of: executing a system initialization on the non-volatile memory to obtain a remaining storage capacity; selecting a number from a lookup table as an initial storage capacity according to the remaining storage capacity and a lookup table; and referring the initial storage capacity as a fixed capacity in the data storage device and writing the initial storage capacity into the non-volatile memory. A lookup table generating method and the data storage device are also provided.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: July 2, 2019
    Assignee: Silicon Motion, Inc.
    Inventor: Sheng-Yuan Huang
  • Patent number: 10331474
    Abstract: A machine system includes a physical machine, a memory pool, and a memory pool management machine. The memory pool management machine manages, with respect to a memory region of the memory pool, an allocated region, a cleared region, and an uncleared region. When generating a virtual machine, a hypervisor in the physical machine sends a memory allocation request to the memory pool management machine. When a response, to the request, received from the memory pool management machine includes an address range belonging to the uncleared region, the hypervisor clears the memory region of the address range belonging to the uncleared region and then generates the virtual machine.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: June 25, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Imada, Toshiomi Moriki
  • Patent number: 10331560
    Abstract: Methods and systems for providing cache coherence in multi-compute-engine systems are described herein. In on example, concise cache coherency directory (CDir) for providing cache coherence in the multi-compute-engine systems is described. The CDir comprises a common pattern aggregated entry for one or more cache lines from amongst a plurality of cache lines of a shared memory. The one or more cache lines that correspond to the common pattern aggregated entry are associated with a common sharing pattern from amongst a predetermined number of sharing patterns that repeat most frequently in the region.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: June 25, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Jichuan Chang, Sheng Li
  • Patent number: 10331583
    Abstract: A processing device for executing distributed memory operations using spatial processing units (SPU) connected by distributed channels is disclosed. A distributed channel may or may not be associated with memory operations, such as load operations or store operations. Distributed channel information is obtained for an algorithm to be executed by a group of spatially distributed processing elements. The group of spatially distributed processing elements can be connected to a shared memory controller. For each distributed channel in the distributed channel information, one or more of the group of spatially distributed processing elements may be associated with the distributed channel based on the algorithm. By associating the spatially distributed processing elements to a distributed channel, the functionality of the processing element can vary depending on the algorithm mapped onto the SPU.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Bushra Ahsan, Michael C. Adler, Neal C. Crago, Joel S. Emer, Aamer Jaleel, Angshuman Parashar, Michael I. Pellauer
  • Patent number: 10324851
    Abstract: Facilitating recording a trace of code execution using way-locking in a set-associative processor cache. A computing device reserves cache line(s) in set(s) of cache lines of a set-associative cache for caching only locations in the system memory that are allocated to a particular executable entity. During a traced execution of the particular executable entity, the computing device detects that a cache miss has occurred on a location in the system memory that is allocated to a particular executable entity, and that a value at the location of system memory is being cached into one of the reserved cache lines. Based on the value at the location of system memory being cached into a reserved cache line, the computing device logs into a trace data stream at least a portion of the value at the location of system memory being cached into the reserved cache line.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: June 18, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Jordi Mola
  • Patent number: 10324860
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 18, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Patent number: 10319004
    Abstract: Techniques for medical coding include applying a natural language understanding (NLU) engine to a free-form text documenting a clinical patient encounter, to derive a first set of one or more medical billing codes for the clinical patient encounter and a link between each code in the first set and a corresponding portion of the free-form text. The first set of codes may be compared to a second set of one or more medical billing codes approved by one or more human users for the patient encounter, to identify at least one code in the first set that overlaps with at least one code in the second set. The code in the second set approved by the one or more human users may be retained instead of the overlapping code in the first set derived by the NLU engine.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: June 11, 2019
    Assignee: Nuance Communications, Inc.
    Inventors: Gregory Reiser, Howard D'Souza, Aparna Subramanian, Regina Spitznagel
  • Patent number: 10318205
    Abstract: A method for managing data using a number of non-volatile memory arrays is described. The method includes writing data from a volatile memory region to a first non-volatile memory array. The method also includes writing a remaining portion of the data from the volatile memory region to a second non-volatile memory array in response to detecting that an event has occurred. The second non-volatile memory array has a lower write latency than the first non-volatile memory array.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: June 11, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Martin Foltin
  • Patent number: 10311534
    Abstract: A tool for planning and management of clinical trials. The tool computes a patient enrollment timeline in a clinical trial using multiple factors that bear on the rate of patient enrollment. The factors may be site-dependent factors or may be country-dependent factors. When these factors are applied, different sites may have different rates of enrollment in the same interval. Further, the factors may be time dependent such that even the same sites may have different enrollment rates in different intervals. Once the timeline is created, the tool may use it to calculate a schedule of monitor visits, project trial completion or otherwise generate output used in management of the clinical trial.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: June 4, 2019
    Assignee: PAREXEL INTERNATIONAL CORPORATION
    Inventor: Joshua Schultz
  • Patent number: 10303615
    Abstract: In one example in accordance with the present disclosure, a system may comprise a memory accessor to access a memory and a pointer loader to load a virtual address (VA) pointer corresponding to a first location in the memory and a physical address (PA) pointer corresponding to the VA pointer. The system may comprise a pointer handler to determine a first physical address in the memory mapped to the first location in the memory and a location matcher to determine whether the second physical address mapped to the PA pointer matches the first physical address. The system may also comprise an exception handler to raise an exception when the second physical address does not match the first physical address.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: May 28, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Dejan S. Milojicic, Moritz J. Hoffmann, Alexander Richardson
  • Patent number: 10303362
    Abstract: A method, non-transitory computer readable medium, and device that assists with reducing initialization duration and performance impact during configuration of storage drives includes identifying a plurality of new storage drives in a storage system. Next, one or more zeroed out storage drives is identified from the identified plurality of new storage drives based on information present in a data portion of each the identified plurality of new storage drives. A volume group comprising the identified one or more zeroed out drives is created and this created volume group is provided for data operation.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: May 28, 2019
    Assignee: NETAPP, INC.
    Inventors: Mahmoud K. Jibbe, Charles Binford
  • Patent number: 10296454
    Abstract: The systems described herein are configured to enhance the efficiency of memory in a host file system with respect to hosted virtual file systems. In situations when the hosted virtual file systems use smaller file block sizes than the file block sizes of the host file system. During storage of a file, a file block is assigned a block address and unmapping bits. The block address and unmapping bits are stored in a pointer block or other similar data structure associated with the file. Particularly, the block address is stored in a first address block and the unmapping bits are stored in at least one additional address block located in proximity to the block address, such that the unmap granularity of the file is not limited by the fixed size of address blocks in the system.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: May 21, 2019
    Assignee: VMware, Inc.
    Inventors: Prasad Rao Jangam, Asit Desai, Prasanna Aithal, Bryan Branstetter, Mahesh S Hiregoudar, Srinivasa Shantharam, Pradeep Krishnamurthy, Raghavan Pichai, Rohan Pasalkar
  • Patent number: 10297344
    Abstract: Systems and methods are provided for generating an individual's longitudinal medication history. Consent to generate an individual's longitudinal medication history across a pharmacy(s) and a claims processor(s) is received. A first collection of medication history data corresponding to the individual is selectively identified from medication history data files associated with the claims processor(s) and a first plurality of individuals. The selective identification is based on a claims processor patient identifier(s) associated with the individual and the claims processor(s). A second collection of medication history data corresponding to the individual is selectively identified from medication history data files associated with the pharmacy(s) and a second plurality of individuals. The selective identification is based on a linking index(s) associated with the claims processor patient identifier(s).
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 21, 2019
    Assignee: MCKESSON CORPORATION
    Inventors: Mark Beers, Elke Helga Katharina Timmerman, James Adair
  • Patent number: 10289561
    Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 14, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Elona Erez, Avner Dor, Jun-Jin Kong
  • Patent number: 10289567
    Abstract: A system for managing cache utilization includes a processor core, a lower-level cache, and a higher-level cache. In response to activating the higher-level cache, the system counts lower-level cache victims evicted from the lower-level cache. While a count of the lower-level cache victims is not greater than a threshold number, the system transfers each lower-level cache victim to a system memory without storing the lower-level cache victim to the higher-level cache. When the count of the lower-level cache victims is greater than the threshold number, the system writes each lower-level cache victim to the higher-level cache. In this manner, if the higher-level cache is deactivated before the threshold number of lower-level cache victims is reached, the higher-level cache is empty and thus may be deactivated without flushing.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 14, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: William L. Walker
  • Patent number: 10289342
    Abstract: A method includes detecting triggering of establishing a data access optimization protocol for at least a portion of a dispersed storage network (DSN). The establishing the data access optimization protocol includes determining an error rate parameter based on subscription data regarding the at least a portion of the DSN, determining system error rate of the at least a portion of the DSN, and establishing a data access threshold plus protocol based on the error rate parameter and the system error rate. The data access threshold plus protocol includes a value greater than a threshold number. When the data access optimization protocol is established, the method further includes generating a set of data access requests for the set of encoded data slices in accordance with the data access optimization protocol, and sending the set of data access requests to a set of storage units affiliated with the at least a portion of the DSN.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jason K. Resch, Greg R. Dhuse, Ravi V. Khadiwala, Wesley B. Leggette
  • Patent number: 10282297
    Abstract: A system comprises a number of master devices and an interconnect for managing coherency between the master devices. In response to a read-with-overridable-invalidate transaction received by the interconnect from a requesting master device requesting that target data associated with a target address is provided to the requesting master device, when target data associated with the target address is stored by a cache, the interconnect issues a snoop request to said cache triggering invalidation of the target data from the cache except when the interconnect or cache determines to override the invalidation and retain the target data in the cache. This enables greater efficiency in cache usage since data which the requesting master considers is unlikely to be needed again can be invalidated from caches located outside the master device itself.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: May 7, 2019
    Assignee: ARM Limited
    Inventors: Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal, Mark David Werkheiser
  • Patent number: 10277408
    Abstract: A method for authorizing I/O (input/output) commands in a storage cluster is provided. The method includes generating a token responsive to an authority initiating an I/O command, wherein the token is specific to assignment of the authority and a storage node of the storage cluster. The method includes verifying the I/O command using the token, wherein the token includes a signature confirming validity of the token and wherein the token is revocable.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: April 30, 2019
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, Robert Lee
  • Patent number: 10275367
    Abstract: Example implementations relate to command source verification. An example device can include instructions executable to send a command via a predefined path to a predefined location within a memory resource storing instructions executable to verify a source of the command using a predefined protocol and execute the command in response to the source verification.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 30, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Maugan Villatel, Richard A. Bramley, Jr., Valiuddin Y. Ali
  • Patent number: 10268383
    Abstract: Two or more read modes of a data storage system and device are defined. The data storage device is capable of concurrently reading from two or more tracks using two or more read transducers. The read modes utilize different numbers of the two or more read transducers while reading data. The read modes are selected based on an operating condition of the data storage system or device.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: April 23, 2019
    Assignee: Seagate Technology LLC
    Inventors: Mehmet Fatih Erden, Scott Warmka, Mark Allen Gaertner, Jon D. Trantham