Abstract: Circuitry that includes a radio frequency (RF) power amplifier (PA) and a dynamic supply boosting circuit, is disclosed. The RF PA receives and amplifies an RF input signal to provide an RF transmit signal using a PA power supply voltage. The dynamic supply boosting circuit provides the PA power supply voltage using a dynamic supply input voltage, wherein when a peak-to-average (PAR) of the RF input signal exceeds a PAR threshold, the dynamic supply boosting circuit boosts the PA power supply voltage, such that the PA power supply voltage is greater than the dynamic supply input voltage.

Abstract: An apparatus includes an RF power amplifier with a controller and an impedance matching network. The RF power amplifier is configured to drive a load in electrical communication with the RF power amplifier. The impedance matching network is located electrically between the RF power amplifier and the load. The impedance matching network is configured to match an output impedance of the RF power amplifier and an impedance of the load. The impedance matching network includes a set of fixed value impedance matching circuits configured to provide different discrete values. The RF amplifier includes a variable DC power supply powering RF transistors to result in a variable output impedance for the amplifier. The controller selects an impedance matching circuit of the capacitor presets and/or the right setting for the variable DC supply that result in minimum reflected power to match the output impedance of the amplifier to the output load impedance.

Abstract: A Doherty amplifier is able to enhance efficiency in low-power and high-power RF communication states by enabling carrier and peaking amplifiers as required, and controlling bias modulation, depending on traffic loading levels in each of a set of consecutive communications timeslots. For example, if, in a low-power state, traffic loading levels do not exceed a relatively lower threshold in a communications timeslot, carrier amplifiers are selectively enabled as needed, peaking amplifiers are not enabled, and carrier amplifier bias levels are kept substantially constant. If, in an intermediate-power state, the lower threshold is exceeded but a relatively higher threshold is not exceeded, all carrier amplifiers are enabled, peaking amplifiers are selectively enabled, and bias levels are kept substantially constant. If, in a high-power state, the higher threshold is exceeded, all carrier and peaking amplifiers can be enabled, and the peaking amplifier bias tracks the RF envelope of the received RF signal.

Abstract: Methods and systems for accurate gain adjustment of a transimpedance amplifier using a dual replica and servo loop is disclosed and may include, in a transimpedance amplifier (TIA) circuit comprising a first TIA, a second TIA, and a third TIA, each comprising a configurable feedback impedance, and a control loop, where the control loop comprises a gain stage with inputs coupled to outputs of the first and second TIAs and an output coupled to the configurable feedback impedance of the second and third TIAs: configuring a gain level of the first TIA by configuring its feedback impedance, configuring a gain level of the third TIA by configuring a reference current applied to an input of the first TIA, and amplifying a received electrical signal to generate an output voltage utilizing the third TIA. The reference current may generate a reference voltage at one of the inputs of the gain stage.

Abstract: Disclosed here is an apparatus that comprises an amplifier having first and second input nodes, first and second resistors, a first electrostatic discharge protection circuit coupled between the first input node and the first resistor, and a second electrostatic discharge protection circuit coupled between the second input node and the second resistor.

Abstract: A multi-frequency tunable low-noise amplifier and a multi-frequency tuning implementation method therefor. The amplifier comprises: a system controller (13) and a micro-electro-mechanical system (MEMS) matching tuner (12) connected to the system controller (13). The system controller (13) is configured to respond to a first operation executed by a user via a user interface (15) when in a first mode, to acquire a first matching value produced on the basis of the first operation, and to output the first matching value to the MEMS matching tuner (12). The MEMS matching tuner (12) is configured to be controlled by the system controller (13) and to support the amplifier working on different frequency bands in tuning processing, thus allowing the matching value of the MEMS matching tuner (12) itself to match a current working frequency band.

Abstract: The present disclosure relates to circuitry including an auto-bias circuit for a stacked FET power amplifier. The auto-bias circuit includes a dividing circuit and an averaging circuit. The dividing circuit is configured to receive a control signal with a control voltage and provide a first pre-gate signal having a first pre-gate voltage that corresponds to a fraction of the control voltage. The averaging circuit is configured to receive the control signal and a supply signal with a supply voltage and provide a second pre-gate signal having a second pre-gate voltage that corresponds to a fraction of a sum of the control voltage and the supply voltage. The stacked power amplifier includes a first FET in series with a second FET. The first FET receives a first gate signal derived from the first pre-gate signal. The second FET receives a second gate signal derived from the second pre-gate signal.

Abstract: A Doherty amplifier of an embodiment includes an input terminal, an output terminal a splitter, a combiner, a carrier amplifier, a peak amplifier. The splitter is connected to the input terminal, the splitter having first and second outputs. The combiner is connected to the output terminal, the combiner having first and second inputs. The carrier amplifier includes a first input-side two-port network connected to the first output of the splitter, a first amplifier connected to an output of the first input-side two-port network, and a first output-side two-port network connected between an output of the first amplifier and the first input of the combiner. The peak amplifier includes a second input-side two-port network connected to the second output of the splitter, a second amplifier connected to the output of the second input-side two-port network, and a second output-side two-port network connected between an output of the second amplifier and the second input of the combiner.

Abstract: The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.

Abstract: An output signal can be free of any noise component generated from an amplifier disposed in a path, without degradation of the S/N ratio of the output signal. An amplifier includes: a first amplifier that is connected to an input node and generates a first intermediate signal; a feedback resistor that enables feedback of the first intermediate signal to the input node; an attenuator that receives the first intermediate signal and generates a second intermediate signal; a second amplifier that is connected to the input node and generates a third intermediate signal; a third amplifier that is connected to the input node and generates a fourth intermediate signal; and an adder that generates an output signal, using the second intermediate signal, the third intermediate signal, and the fourth intermediate signal.

Abstract: An amplifier according to an embodiment of the present disclosure includes a first transistor and a first matching circuit. The first matching circuit is connected between an input terminal and a control terminal of the first transistor. The first matching circuit includes a first inductor, a second inductor, and a first switch. The first inductor has an end connected to the control terminal. The second inductor has an end connected to the other end of the first inductor. The first switch is configured to selectively switch between electrical continuity between the input terminal and the other end of the first inductor and electrical continuity between the input terminal and the other end of the second inductor.

Abstract: An envelope tracking current bias circuit of a power amplifier circuit including a power amplifier includes a first current source circuit configured to generate a first bias current based on a reference voltage, a second current source circuit configured to generate a second bias current based on an envelope voltage of an input signal, and a bias current generator configured to generate a first envelope tracking bias current based on the first bias current and the second bias current, and supply the first envelope tracking bias current to the power amplifier circuit to reduce amplitude modulation-phase modulation (AM-PM) distortion of the power amplifier circuit.

Abstract: Power amplification system is disclosed. A power amplification system can include a Class-E push-pull amplifier including a transformer balun. The power amplification can further include a reactance compensation circuit coupled to the transformer balun. In some embodiments, the reactance compensation circuit is configured to reduce variation over frequency of a fundamental load impedance of the power amplification system.

Abstract: Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition.

Abstract: Provided is a power amplification module that includes: a first amplification circuit that amplifies a first signal and outputs the amplified first signal as a second signal; a second amplification circuit that amplifies the second signal and outputs the amplified second signal as a third signal; and a feedback circuit that re-inputs/feeds back the second signal outputted from the first amplification circuit to the first amplification circuit as the first signal. The operation of the first amplification circuit is halted and the first signal passes through the feedback circuit and is outputted as the second signal at the time of a low power output mode.

Abstract: A two-stage amplifier of a type of the current re-use configuration is disclosed. The amplifier includes first to third transistors, where the first transistor constitute the first stage, while, the latter two transistors constitute the second stance. The first to third transistors are connected in series between a power supply and ground such that a bias current supplied to the third transistor flows in the second and first transistors. The first transistor in the source thereof is grounded in the DC mode. The second transistor is grounded in the AC mode but floated in the DC mode. The third transistor that outputs an amplified signal is connected in parallel in the AC mode but in series in the DC mode with respect to the second transistor.

Abstract: This disclosure provides isolation for a medical amplifier by providing a low impedance path for noise across an isolation barrier. The low impedance path can include a capacitive coupling between a patient ground, which is isolated from control circuitry, and a functional ground of an isolation system that is isolated from earth ground. The low impedance path can draw noise current from an input of an amplifier of patient circuitry.

Abstract: A signal processing system for producing a load voltage at a load output of the signal processing system, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, and may include a first processing path configured to process a first signal derived from an input signal to generate the first load voltage at a first processing path output, a second processing path configured to process a second signal received at a second processing path input and derived from the input signal, wherein the second signal comprises information of the input signal absent from the first signal, to generate the second load voltage at a second processing path output, and a high-pass filter coupled between the first processing path output and the second processing path input.

Abstract: An integrated circuit and method for providing a variable gain amplifier are disclosed. One embodiment of the a variable gain amplifier comprises at least one load, a cascode circuit coupled to the load, a folded-gilbert stage, coupled to the cascode circuit, the folded-gilbert stage comprising a main differential pair of transistors and an internal pair of transistors, and a digital to analog converter, coupled to the folded-gilbert stage, for steering currents between the main differential pair of transistors and the internal pair of transistors to change a gain of the variable gain amplifier.

Abstract: A power amplifier module includes a first amplifier that amplifies an input signal to generate a first amplified signal and outputs the first amplified signal, a second amplifier that amplifies the first amplified signal to generate a second amplified signal and outputs the second amplified signal, and a matching network disposed between an output terminal of the first amplifier and an input terminal of the second amplifier. The first amplifier is provided on a first chip, and the second amplifier is provided on a second chip. The matching network has an impedance transformation characteristic adjustable in accordance with a control signal.