Patents Examined by Hieu P Nguyen
  • Patent number: 10601386
    Abstract: An automatic gain control circuit for controlling an LNA for inputting signals carrying packets, the automatic gain control circuit can perform a background calibration in the non-preamble time region of a first packet for pre-determining a gain adjustment to the LNA before the next preamble of a second packet arrives, so that the gain of the LNA can be adjusted immediately according to the pre-determined gain adjustment when the next preamble of the second packet arrives.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: March 24, 2020
    Assignee: Rafael Microelectronics, Inc.
    Inventors: Meng-Ping Kan, Kuan-Ming Chen, Benjamin Chiang, Tzy-Yun Wang
  • Patent number: 10594278
    Abstract: An amplifier circuit. In some embodiments, the amplifier circuit includes: a telescopic amplifier, and a common mode feedback amplifier. The telescopic amplifier has a first signal input, a second signal input, a first output, a second output, a common mode feedback input, a first pole-splitting capacitor, and a second pole-splitting capacitor. The common mode feedback amplifier has an output connected to the common mode feedback input of the telescopic amplifier. The first pole-splitting capacitor is connected between the common mode feedback input of the telescopic amplifier and the first output of the telescopic amplifier, and the second pole-splitting capacitor is connected between the common mode feedback input of the telescopic amplifier and the second output of the telescopic amplifier.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Vaibhav Tripathi
  • Patent number: 10594273
    Abstract: A power amplifier module includes a first amplifier that amplifies an input signal to generate a first amplified signal and outputs the first amplified signal, a second amplifier that amplifies the first amplified signal to generate a second amplified signal and outputs the second amplified signal, and a matching network disposed between an output terminal of the first amplifier and an input terminal of the second amplifier. The first amplifier is provided on a first chip, and the second amplifier is provided on a second chip. The matching network has an impedance transformation characteristic adjustable in accordance with a control signal.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 17, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shingo Yanagihara
  • Patent number: 10587228
    Abstract: An amplifier circuit can have a differential input. A common-mode signal present at the differential input can induce an offset voltage at an output of the amplifier circuit. A compensation can be performed to reduce or eliminate such an offset, such as at a first temperature. Circuits and techniques for drift correction can be performed, such as to correct for residual offset error across an entirety of a specified operation temperature range. In an example, first and second drift correction signal generator circuits can be used, such as to provide signals proportional to a common mode voltage, but having different temperature coefficients.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: March 10, 2020
    Assignee: Analog Devices, Inc.
    Inventor: Quan Wan
  • Patent number: 10587235
    Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 10, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sudheer Prasad
  • Patent number: 10581396
    Abstract: Provided is an electric transmission cable module that has both a squelch function and an AGC function, and realizes a highly accurate function while suppressing an increase in chip cost.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: March 3, 2020
    Assignee: Hitachi Metals, Ltd.
    Inventors: Koji Maeda, Izumi Fukasaku
  • Patent number: 10581387
    Abstract: An improved architecture for a radio frequency (RF) power amplifier, impedance matching network, and selector switch. One aspect of embodiments of the invention is splitting the functionality of a final stage impedance matching network (IMN) into two parts, comprising a base set of off-chip IMN components and an on-chip IMN tuning component. The on-chip IMN tuning component may be a digitally tunable capacitor (DTC). In one embodiment, an integrated circuit having a power amplifier, an on-chip IMN tuner, and a selector switch is configured to be coupled to an off-chip set of IMN components. In another embodiment, an integrated circuit having an on-chip IMN tuner and a selector switch is configured to be coupled through an off-chip set of IMN components to a separate integrated circuit having an RF power amplifier.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: March 3, 2020
    Assignee: pSemi Corporation
    Inventors: Tero Tapio Ranta, Chih-Chieh Cheng, Kevin Roberts
  • Patent number: 10566936
    Abstract: Various technologies pertaining to a high-impedance current source are described herein. The current source outputs a substantially constant current by way of a first transistor that draws current from a supply. The current source is configured to feed-back noise from the supply to a feedback resistor at an input of an operational amplifier (op-amp) by way of a second transistor. The feedback resistor and the op-amp are configured such that responsive to receiving the supply noise feedback, the op-amp drives a gate voltage of the first transistor to cause the first transistor to reject the supply noise and cause the output of the current source to remain substantially constant.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: February 18, 2020
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventor: Kurt O. Wessendorf
  • Patent number: 10566943
    Abstract: Apparatus and methods for biasing of power amplifiers are disclosed. In one embodiment, a mobile device includes a transceiver that generates a radio frequency signal and a power amplifier enable signal, a power amplifier that provides amplification to the radio frequency signal and that is biased by a bias signal, and a bias circuit that receives the power amplifier enable signal and generates the bias signal. The bias circuit includes a gain correction circuit that generates a correction current in response to activation of the power amplifier enable signal, and a primary biasing circuit that generates the bias signal based on the correction current and the power amplifier enable signal.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 18, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Ping Li, Paul T. DiCarlo
  • Patent number: 10541604
    Abstract: Techniques for supplying a bias current to a load are provided. In certain examples, a circuit can include a level-shift capacitance, a current source, and a load configured to receive a bias current in a first state of the circuit. The current source and the level-shift capacitance can be coupled in series between the load and a supply voltage in the first state. In some examples, during a second state of the circuit, the level-shift capacitance can receive charge, and can be isolated from one of the load or the current source.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: January 21, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Christopher Peter Hurrell, Derek J. Hummerston
  • Patent number: 10530310
    Abstract: Digital pre-distortion may be provided. First, a radio frequency (RF) domain distortion correcting signal and a base band (BB) domain distortion correcting signal may be initialized. Then the RF domain distortion correcting signal may be generated from an input signal. The generated RF domain distortion correcting signal may correspond to an amplifier. Next, the BB domain distortion correcting signal may be generated from the input signal. The generated BB domain distortion correcting signal may correspond to the amplifier. Then the RF domain distortion correcting signal and the BB domain distortion correcting signal may be combined to form a hybrid distortion correcting signal. The hybrid distortion correcting signal may then be provided to input matching circuitry feeding the amplifier.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: January 7, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Hang Jin, John T. Chapman
  • Patent number: 10530309
    Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: January 7, 2020
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd
    Inventors: Ru Feng Du, Qi Yu Liu
  • Patent number: 10523164
    Abstract: A semiconductor integrated circuit including a differential amplifier circuit, a first output circuit, a second output circuit, a selection circuit, and a feedback circuit. The differential amplifier circuit is configured to operate at a first source voltage. The first output circuit is configured to receive an output of the differential amplifier circuit, output a first output, and operate at the first source voltage. The second output circuit is configured to receive an output of the differential amplifier circuit, output a second output, and operate at a second source voltage lower than the first source voltage. The selection circuit is configured to select one of the first output from the first output circuit and the second output from the second output circuit according to an operating phase determined by an external control signal. The feedback circuit is connected between the differential amplifier circuit and the selection circuit.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: December 31, 2019
    Assignee: RICOH COMPANY, LTD.
    Inventors: Sho Kamezawa, Tohru Kanno
  • Patent number: 10516367
    Abstract: The present disclosure relates to a logic control circuit including a first inverter and a voltage limiter. The first inverter is connected to a first input voltage. The first inverter includes a first transistor having a first terminal and a second terminal. The second terminal of the first transistor is connected to a ground. The voltage limiter includes a second transistor. The second transistor has a gate connected to a ground, a source connected to the first terminal of the first transistor and a drain connected to a second input voltage.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: December 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Jaw-Ming Ding
  • Patent number: 10516372
    Abstract: A switching amplifier circuit (200) connected to drive an impedance-based output load (230) includes high side and low side switches (201-204) configured and connected to connect first and second supply voltage lines to first and second output nodes (ANTP, ANTN) in response to gating control signals, and also includes an output current sensing circuit for measuring a current through the output load with a current sensing resistor (Rs) connected between the second supply voltage line and a source of one or more split gate-source switching transistors (203C) in the low side gate-source switching transistor, where a voltage sense circuit connected across the current sensing resistor is configured to sample a voltage across the current sensing resistor for measuring a sense current at the current sensing resistor.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: December 24, 2019
    Assignee: NXP B.V.
    Inventors: Hermanus J. Effing, Dimitar M. Dochev, Maarten J. Swanenberg
  • Patent number: 10516368
    Abstract: Fast envelope tracking systems are provided herein. In certain embodiments, an envelope tracking system for a power amplifier includes a switching regulator and a differential error amplifier configured to operate in combination with one another to generate a power amplifier supply voltage for the power amplifier based on an envelope of a radio frequency (RF) signal amplified by the power amplifier. The envelope tracking system further includes a differential envelope amplifier configured to amplify a differential envelope signal to generate a single-ended envelope signal that changes in relation to the envelope of the RF signal. Additionally, the differential error amplifier generates an output current operable to adjust a voltage level of the power amplifier supply voltage based on comparing the single-ended envelope signal to a reference signal.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 24, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Florinel G. Balteanu, Serge Francois Drogi, Sabah Khesbak, Hardik Bhupendra Modi
  • Patent number: 10511276
    Abstract: A signal amplifier is distributed between first and second IC devices and includes a low-power input stage disposed within the first IC device, a bias-current source disposed within the second IC device and an output stage disposed within the second IC device. The output stage includes a resistance disposed within the second IC device and having a first terminal coupled to a drain terminal of a transistor within the input stage via a first signaling line that extends between the first and second IC devices.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 17, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Carl W. Werner, John Eric Linstadt
  • Patent number: 10511264
    Abstract: The present invention relates to a method, of providing adaptive impedance in a Power Amplifier (PA), by providing more than one transistors in which one transistor is used to change the load line or to linearize the input signal by adapting the biasing of each transistor, wherein the transistors are connected in parallel.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: December 17, 2019
    Inventor: Ofer Gepstein
  • Patent number: 10498292
    Abstract: An amplifier module is provided. The amplifier module includes a multi-layer printed circuit board (PCB). A first power transistor die is mounted at a top surface of the multi-layer PCB. A second power transistor die is mounted at the top surface of the multi-layer PCB. An impedance inversion element is coupled between an output of the first power transistor die and an output of the second power transistor die. A combining node is formed at the output of the second power transistor die. A stub circuit including a transmission line element is coupled at the combining node.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 3, 2019
    Assignee: NXP USA, INC.
    Inventors: Enver Krvavac, Joseph Gerard Schultz, Yu-Ting David Wu, Nick Yang
  • Patent number: 10498291
    Abstract: A bias circuit and a power amplifier circuit are provided in the present disclosure. The bias circuit includes an output node, a power detecting circuit, a first constant voltage bias circuit, and a constant current bias circuit. The output node is configured to provide a bias signal to a power amplifier unit. The output node is further configured to receive an input signal of the power amplifier unit. The power detecting circuit is configured to detect a power of the input signal of the power amplifier unit to provide a first control signal. The first constant voltage bias circuit is configured to selectively provide a first signal to the output node according to the first control signal. The constant current bias circuit provides a second signal to the output node.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: December 3, 2019
    Assignee: AIROHA TECHNOLOGY CORP.
    Inventor: Li-Fan Tsai