Patents Examined by Hoa B. Trinh
  • Ear-loop earphone
    Patent number: 8837766
    Abstract: According to an exemplary embodiment of the present disclosure, the ear-loop earphone comprises a main body, an ear-loop base and an ear-loop. The main body has a surrounding side, a front side, and a back side, wherein the front side is opposing to the back side, the front side has a plurality of sounding apertures for outputting an audio, and the surrounding side surrounds and connects to the front side and the back side. The ear-loop base is fixed on the surrounding side of the main body in a rotatable manner, and rotates with respect to a first axis. The ear-loop is fixed on the ear-loop base in a rotatable manner, and rotates with respect to a second axis different from the first axis.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: September 16, 2014
    Assignee: Lite-On Technology Corporation
    Inventors: Chun-Hsin Liu, Shu-Yuan Cheng
  • Semiconductor package and method of manufacturing the same
    Patent number: 8828796
    Abstract: A semiconductor package and a method of manufacturing the same are provided, the semiconductor package including a first package unit having a first encapsulant and a first semiconductor element, a second package unit having a second encapsulant and a second semiconductor element, a supporting member interposed between the first and second encapsulant, a plurality of conductors penetrating the first encapsulant, the supporting member and the second encapsulant, and redistribution structures disposed on the first and second encapsulants, wherein the first and second encapsulants are coupled with each other by the supporting member to provide sufficient support and protection to enhance the structure strength of the first and second package units.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: September 9, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chieh-Yuan Chi, Wei-Yu Chen, Hung-Wen Liu, Yan-Heng Chen, Hsi-Chang Hsu
  • Fiber-containing resin substrate, sealed substrate having semiconductor device mounted thereon, sealed wafer having semiconductor device formed thereon, a semiconductor apparatus, and method for manufacturing semiconductor apparatus
    Patent number: 8823186
    Abstract: A fiber-containing resin substrate for collectively sealing a semiconductor devices mounting surface of a substrate having the semiconductor devices mounted thereon or a semiconductor devices forming surface of a wafer having semiconductor devices formed thereon, includes: a resin-impregnated fiber base material obtained by impregnating a fiber base material with a thermosetting resin and semi-curing or curing the thermosetting resin; and an uncured resin layer containing an uncured thermosetting resin and formed on one side of the resin-impregnated fiber base material.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: September 2, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Susumu Sekiguchi, Toshio Shiobara
  • Electronic device package and method for fabricating the same
    Patent number: 8823179
    Abstract: An embodiment of the present invention provides an electronic device package, which includes a chip having a first surface and an opposite second surface and a trench extending into a body of the chip along a direction from the second surface to the first surface, wherein a bottom portion of the trench includes at least two contact holes.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: September 2, 2014
    Inventors: Chia-Lun Tsai, Wen-Cheng Chien, Po-Han Lee, Wei-Ming Chen, Chien-Hung Liu, Ying-Nan Wen
  • TSV structures and methods for forming the same
    Patent number: 8803316
    Abstract: A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Wen-Chih Chiou, Ku-Feng Yang, Tsang-Jiuh Wu, Jing-Cheng Lin
  • Semiconductor chips including passivation layer trench structure
    Patent number: 8803318
    Abstract: An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Deepak Kulkarni, Michael W. Lane, Satyanayana V. Nitta, Shom Ponoth
  • Semiconductor wafer and semiconductor device wafer
    Patent number: 8796820
    Abstract: A semiconductor wafer having a disc shape includes a chamfer provided around a circumferential edge of the wafer, and an anti-cracking and chipping groove provided in one or more areas around one circumference of an end face of the wafer along a circumferential direction of the end face. The anti-cracking and chipping groove is configured to prevent cracking or chipping of the end face in back grinding.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: August 5, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventors: Shusei Nemoto, Hisashi Mashiyama
  • Circuit board and chip package structure
    Patent number: 8796848
    Abstract: A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: August 5, 2014
    Assignee: Via Technologies, Inc.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Yeh-Chi Hsu
  • RFID tags with bumped substrate, and apparatuses and methods for making
    Patent number: 8796865
    Abstract: Radio Frequency Identification (RFID) tags are provided, along with apparatuses and methods for making. In some embodiments, the RFID tags include an RFID tag chip that is attached to an inlay and/or a strap. The inlay or strap has one or more contact bumps formed thereon. In some of these embodiments, the RFID tag chip includes pads for electrical contacts, but not chip-bumps, thanks to the contact bump.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: August 5, 2014
    Assignee: Impinj, Inc.
    Inventors: Jay M. Fassett, Ronald A. Oliver, Ronald L. Koepp, Steven I. Mozsgai, Ernest Allen, III
  • Semiconductor device
    Patent number: 8791567
    Abstract: In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r3 from the circumference of the opening pattern to the central axis of the through-hole is smaller than the distance r1 in the through-hole. By providing the opening pattern, the conductive pattern is exposed at the bottom surface of the through-hole. The bump is located on the back surface side of the substrate, and is formed integrally with the through-electrode.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: July 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuaki Takahashi, Masahiro Komuro, Satoshi Matsui
  • Integrated circuit package with voltage distributor
    Patent number: 8791582
    Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: July 29, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chu-Chung Lee, Kian Leong Chin, Kevin J. Hess, Patrick Johnston, Tu-Anh N. Tran, Heng Keong Yip
  • Semiconductor device and method for manufacturing semiconductor device
    Patent number: 8786106
    Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: July 22, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi
  • Semiconductor device and method of manufacturing same
    Patent number: 8785919
    Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: July 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Hideaki Kuwabara
  • Reacted conductive gate electrodes and methods of making the same
    Patent number: 8785315
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Richard Hammond
  • Headphone device
    Patent number: 8767997
    Abstract: A headphone device including a driver unit, and an ear-hook hanger of a loop shape that is integrated with the driver unit and supports an entire circumference of an ear capsule is provided.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: July 1, 2014
    Assignee: Sony Corporation
    Inventors: Keitaro Fujiwara, Katsunori Murozaki
  • Power line layout techniques for integrated circuits having modular cells
    Patent number: 8766324
    Abstract: An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first memory cell array block do not extend into the second memory cell array block, and all the power lines on the first metal layer serving the second memory cell array block do not extend into the first memory cell array block.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Cheng Hung Lee
  • Repairable semiconductor device and method
    Patent number: 8754522
    Abstract: Repairable semiconductor device and method. In one embodiment a method, provides a first body having a first semiconductor chip and a first metal layer. A second body includes a second semiconductor chip and a second metal layer. Metal of the first metal layer is removed. The first semiconductor chip is removed from the first body. The second body is attached to the first body. The first metal layer is electrically coupled to the second metal layer.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: June 17, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gerald Ofner
  • Structure and method for E-beam in-chip overlay mark
    Patent number: 8736084
    Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dong-Hsu Cheng, Ming-Ho Tsai, Chih-Chung Huang, Yung-Hsiang Chen, Jyun-Hong Chen
  • Alignment accuracy mark
    Patent number: 8729716
    Abstract: An alignment accuracy (AA) mark is described, including N (N?3) pattern sets defined by N exposure steps respectively. The N exposure steps are performed also to a device area disposed on a wafer together with the AA mark. The i-th (i=1, 2 . . . N?1) pattern set surrounds the (i+1)-th pattern set. Each pattern set includes a 1st set of x-directional linear patterns, a 2nd set of x-directional linear patterns arranged opposite to the 1st set of x-directional linear patterns in the y-direction, a 1st set of y-directional linear patterns, and a 2nd set of y-directional linear patterns arranged opposite to the 1st set of y-directional linear patterns in the x-direction, wherein each set of x- or y-directional linear patterns include at least three separate parallel linear patterns.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: May 20, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Lin Chuang, Wen-Liang Huang, Chia-Hung Lin, Chun-Chi Yu
  • Semiconductor package and a method for selecting a chip in the semiconductor package
    Patent number: 8729686
    Abstract: A semiconductor package includes a first semiconductor chip formed with a first through-silicon via; a second semiconductor chip stacked over the first semiconductor chip and formed with a second through-silicon via; and a cantilever formed over the first semiconductor chip and electrically connected to the first through-silicon via or the second through-silicon via according to an electrical signal.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 20, 2014
    Assignee: SK Hynix Inc.
    Inventor: Tae Min Kang