Abstract: A package includes a sensor die with a micro component, such as a MEMS device, coupled to an integrated circuit which may include, for example, CMOS circuitry, and one or more electrically conductive bond pads near the periphery of the sensor die. A semiconductor cap structure is attached to the sensor die. The front side of the cap structure is attached to the sensor die by a seal ring to hermetically encapsulate an area of the sensor die where the micro component is located. The bond pads on the sensor die are located outside the area encapsulated by the seal ring. Electrical leads, which extend along outer side edges of the semiconductor cap structure from its front side to its back side, are coupled to the micro component via the bond pads.

Abstract: An assembly device of an image sensor chip is disclosed. A flexible circuit has a die-attached portion, a plurality of bendable portions, and a plurality of bonding portions where the bendable portions extend from the die-attached portion and are connected to the corresponding bonding portions. A plurality of inner leads are formed on the bonding portions. An image sensor chip with bumps is attached to the die-attached portion. The bendable portions are so bent that the bonding portions are located above the image sensor chip. By thermocompression bonding, the inner leads of the flexible circuit are bonded to the bumps on the image sensor chip. In one embodiment, a transparent cover is adhered to the bonding portions and located above a sensing area of the image sensor chip.

Abstract: A method of driving a solid-state image sensing device comprises plural photoelectric conversion devices arranged in rows and columns perpendicular to the rows, VCCDs through which charges generated by the photoelectric conversion devices are transferred in the column direction, and an HCCD through which the charges transferred from the VCCDs are transferred in the row direction. The photoelectric conversion devices include plural photoelectric conversion device rows including the photoelectric conversion devices arranged in the rows include first photoelectric conversion device rows each of which different kinds of photoelectric conversion devices are mixed and second photoelectric conversion device rows each of which has one kind of photoelectric conversion devices.

Abstract: A dielectric isolation type semiconductor device can achieve high dielectric resistance while preventing the dielectric strength thereof from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A drift N? region is bonded to a semiconductor substrate through a buried oxide film to from a high withstand-voltage device in the drift N? region. A first field plate is formed on the drift N? region in the vicinity of a drain electrode. A first high silicon concentration region composed of a buried N+ region is formed in a porous oxide film region forming a part of the buried oxide film at a location right under the drain electrode. The drain electrode and the first field plate are electrically connected to the first high silicon concentration region through a drain N? well region.

Abstract: Die-down array integrated circuit (IC) device packages with enhanced thermal, electrical, and input/output properties are presented. A die-down array IC device package includes a heat spreader having a central cavity. A first substrate surface is coupled to the heat spreader. A central opening through the substrate overlaps the central cavity. Alternatively, the heat spreader is formed by coupling a ring-shaped body to a planar heat spreader. The first substrate surface is coupled to the ring-shaped body and the substrate central opening overlaps a central opening through the ring-shaped body. An array of electrically conductive terminals is coupled to a second substrate surface. An IC die is mounted to the heat spreader within the central cavity. Bond pads on the die are coupled to corresponding bond pads on the substrate with a plurality of wire bonds. Electrically conductive bumps on the die are coupled to corresponding bond pads on an interposer.

Abstract: Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.

Abstract: An active device array substrate is provided. The active device array substrate comprises a substrate, multiple first lines, second lines, active devices, pixel electrodes and common lines. The first lines and second lines are disposed on the substrate and they form multiple pixel regions on the substrate. The active devices are respectively disposed in the pixel regions and each of the active devices is electrically connected to a first line and a second line, respectively. The pixel electrodes are respectively disposed in the pixel regions and each of the pixel electrodes is electrically connected to an active device, respectively. The common lines and first lines are roughly parallel and they are staggeringly disposed on the substrate. Each of the common lines has multiple branches which extend outside from their edges of two sides, and each of these branches is partly overlapped with the second lines.

Abstract: A wired circuit board having terminals that can ensure large electrical connection areas while preventing shorting of adjacent terminals, to ensure that the terminals are electrically connected with external terminals through molten metal. An insulating base layer 3 is formed on a supporting board 2 so that insulating concave portions 13 are formed at portions thereof where external connecting terminals 8 are to be formed. A conductive pattern 4 is formed on the insulating base layer 3 so that a number of lines of wire 4a, 4b, 4c, 4d, the magnetic head connecting terminals 7, and the external connecting portions 8 are integrally formed, and conductive concave portions 9 are formed in the external connecting terminals 8. Thereafter, an insulating cover layer 10 is formed on the insulating base layer 3 so that the magnetic head connecting terminals 7 and the external connecting terminals 8 are exposed from the insulating cover layer 10.

Abstract: On an insulating substrate, a first insulating buffer layer, a heat accumulating-light shielding layer having at least a silicon layer on the surface thereof, a second insulating buffer layer and a first silicon layer are laminated in the order recited from the bottom. The lamination structure of the heat accumulating-light shielding layer, second buffer layer and first silicon layer is patterned. A laser beam is applied the patterned first silicon layer to melt and crystallize the first silicon layer. A thin film transistor is formed by using the crystallized first silicon layer. A polysilicon thin film transistor of high performance and small leak current to be caused by light as well as a display device using such thin film transistors is provided.

Abstract: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.

Abstract: A semiconductor device (1) of the present invention includes a semiconductor element (103) including electrode parts (104), and a wiring substrate (108) including an insulation layer (101), electrode-part-connection electrodes (102) provided in the insulation layer (101), and external electrodes (107) that is provided in the insulation layer (101) and that is connected electrically with the electrode-part-connection electrodes (102), in which the electrode parts (104) and the electrode-part-connection electrodes (102) are connected electrically with each other. The insulation layer (101) has an elastic modulus measured according to JIS K6911 of not less than 0.1 GP a and not more than 5 GPa, and the electrodes (104) and the electrode-part-connection electrodes (102) are connected by metal joint.

Abstract: The invention relates to an electronic module having plug contacts, which has a semiconductor chip embedded in a plastics composition with its rear side and its edge sides. An active top side of the semiconductor chip forms, together with the plastics composition, an overall top side, there being arranged on the latter a rewiring layer with plug contact areas and rewiring lines that connect the plug contact areas to contact areas of the top side of the semiconductor chip.

Abstract: A micro-electro-mechanical system (MEMS) package having a hydrophobic layer is disclosed. The MEMS package includes: a base substrate, with an MEMS element provided on a surface of the base substrate; a lid, spaced apart from the MEMS element provided on the base substrate and covering the MEMS element; a side sealing member provided on a side surface of the base substrate and the surface of the lid, thus hermetically sealing the MEMS element from an external environment; and a hydrophobic layer which covers the part of the side sealing member that is exposed to the external environment, thus removing the hydrophilia from the side sealing member.

Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the first capacitor electrode. The capacitor dielectric region has an exposed oxide containing surface. The exposed oxide containing surface of the capacitor dielectric region is treated with at least one of a borane or a silane. A second capacitor electrode is deposited over the treated oxide containing surface. The second capacitor electrode has an inner metal surface contacting against the treated oxide containing surface. Other aspects and implementations are contemplated.

Abstract: A light-emitting diode chip (1), in which over a substrate (2), a series of epitaxial layers (3) with a radiation-emitting active structure (4) based on InGaN is disposed. Between the substrate (2) and the active structure (4), a buffer layer (20) is provided. The material or materials of the buffer layer (20) are selected such that their epitaxial surface (6) for the epitaxy of the active structure (4) is unstressed or slightly stressed at their epitaxial temperature. The active structure (4) has In-rich zones (5), disposed laterally side by side relative to the epitaxial plane, in which zones the In content is higher than in other regions of the active structure (4). A preferred method for producing the chip is disclosed.

Abstract: A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate. The lower sidewall portion has a lower sidewall angle. The upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion. By forming the feature with a shallower sidewall angle at the top of the feature, any debris within the feature is more susceptible to rinsing, etching, or other cleaning procedures, and thus the feature is more easily cleaned than standard features having relatively steeper sidewalls.

Abstract: A multi-chip image sensor module includes a flexible module board, an image sensor chip, a transparent cover, and at least an IC chip. The flexible module board has a first die-attached portion, a second die-attached portion, at least one bent portion, and at least one bonding portion where the bent portion connects the first die-attached portion and the bonding portion. The image sensor chip is attached to the first die-attached portion and the IC chip is disposed on the second die-attached portion. Inner leads on the bonding portion are electrically connected to the bonding pads of the image sensor chip when the bonding portion is bonded on the image sensor chip. The transparent cover is disposed above the sensing area of the image sensor chip, preferably adhered to the bonding portion.

Abstract: A micro-electro-mechanical system (MEMS) package having a metal sealing member is disclosed. The MEMS package is formed by forming a metal layer on a substrate by patterning so that the metal layer surrounds an MEMS element provided on the substrate; joining a lid to the metal layer; providing a side sealing member on a side surface of the substrate; and covering the lid and the substrate with a metal sealing member, thus hermetically sealing the MEMS element from the external environment.

Abstract: In a circuit to drive driven elements such, as electro-optical elements, an electro-optical device has an element layer, a wire-forming layer, and an electronic component layer in order to suppress variation in characteristics of active elements. The element layer has a plurality of organic EL elements, each of which is arranged in a different position in a plane. The electronic component layer has pixel-driving IC chips. The respective pixel-driving IC chips include a plurality of pixel circuits, each of which drives each organic EL element corresponding to the pixel circuit. The wire-forming layer is positioned between the element layer and the electronic component layer. The wire-forming layer has wires to connect the respective pixel circuits included in the pixel-driving IC chips with the organic EL elements corresponding to the pixel circuits.

Abstract: A semiconductor device, comprising: a semiconductor substrate in which an integrated circuit is formed, the semiconductor substrate having an electrode electrically connected to the integrated circuit; a resin layer formed on a face in which the electrode of the semiconductor substrate is formed, as to avoid the electrode; a wiring formed as to have a protruding portion projecting upwards on the resin layer, the wiring being electrically connected to the electrode; and a solder formed on the protruding portion of the wiring, wherein the upper face portion of the protruding portion is melt-eroded by the solder and the material of the protruding portion.