Abstract: A process of manufacturing a semiconductor device comprising the step of chemical mechanical polishing for flattening an interlayer insulating film deposited on a wafer on which desired elements are in advance formed, wherein a stopper layer is formed on a region which will be excessively polished through the chemical mechanical polishing before or after forming the interlayer insulating film.

Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.

Abstract: A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist over the non-silicon containing photoresist layer; exposing said silicon containing photoresist layer to an activating light source an exposure surface defined by an overlying pattern according to a photolithographic process; developing said silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least oxygen, carbon monoxide, and argon.

Abstract: In one exemplary embodiment, a structure comprises a substrate having a core, a top surface and a bottom surface. A substrate die pad is situated on the top surface of the substrate and is capable of receiving a die, and a heat spreader is situated on the bottom surface of the substrate. The substrate further comprises a first metal cap, at least one buried via, and a second metal cap. The first metal cap is situated below and is thermally coupled to the substrate die pad. The at least one buried via is situated below the first metal cap within the core of the substrate. The second metal cap is situated below the at least one buried via and is thermally coupled to the second metal cap.

Abstract: The present invention provides a Schottky Structure in gallium arsenide (GaAs) semiconductor device, which comprises a gallium arsenide (GaAs) semiconductor substrate, a titanium (Ti) layer on a surface of said gallium arsenide (GaAs) semiconductor substrate to form Schottky contact, a diffusion barrier layer on a surface of said titanium (Ti) layer to block metal diffusion, and a first copper layer on a surface of said diffusion barrier layer.

Abstract: In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

Abstract: A metal thin film of a semiconductor device and method for forming the same is disclosed, in which excellent step coverage and surface roughness are maintained. The metal thin film of a semiconductor device according to the present invention includes: a barrier metal layer formed on a semiconductor substrate; and a PVD seed thin film, a CVD thin film, and a PVD reflow thin sequentially formed on the barrier metal layer, wherein the PVD seed thin film, the CVD thin film and the PVD reflow thin film are of the same material.

Abstract: The invention relates to a method of manufacturing implanted-base, double polysilicon bipolar transistors whose emitter, base and collector are all situated in a single active area. In accordance with the method, first the island isolation (3) defining the active area (4) in the silicon body (1) is provided, which active area forms the collector (5). A first polysilicon layer (6) is deposited on the surface. A first part (6a) of poly I is p-type doped, a second part is n-type doped. By etching, two separate parts are formed from the first poly layer, one part being p-type doped and forming a base terminal (8), the other part being n-type doped and forming a collector terminal (9), said two parts being separated by an intermediate region (16) where the surface of the active area is exposed. The edges of these poly terminals and the exposed parts of the active area are provided with spacers (13, 15) and spacers (14, 16), respectively.

Abstract: The present invention is generally directed to doping methods for fully-depleted SOI structures, and a device comprising such resulting doped regions. In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the transistor being comprised of a gate electrode, the bulk substrate being doped with a dopant material at a first concentration level. The device further comprises a first doped region formed in the bulk substrate, the first doped region being doped with a dopant material that is the same type as the bulk substrate dopant material, wherein the concentration level of dopant material in the first doped region is greater than the first dopant concentration level in the bulk substrate, the first doped region being substantially aligned with the gate electrode.

Abstract: Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.

Abstract: An in-line system having an overlay measurement function and a method thereof capable of reducing overlay measurement time and simplifying related jobs are disclosed. The system for performing wafer processing comprises an in-line system comprising a stepper for performing alignment and photo-exposure of a wafer and a spinner, in-line connected to the stepper, for performing coating and development of the wafer, and an overlay measurement device, in-line connected to the spinner, for automatically measuring an overlay accuracy of the wafer after wafer development is completed by the spinner.

Abstract: A semiconductor device comprises: a semiconductor substrate on which a silicon germanium film, a carbon-containing silicon film and a silicon film are formed in this order and a gate electrode on the semiconductor substrate with intervention of a gate oxide film, wherein a channel region of the semiconductor device the is formed in the carbon-containing silicon film or wherein a channel region of the semiconductor device is formed in the silicon germanium film.

Abstract: A light emitting diode is disclosed which can enhance the scattering of light produced by a light emitting element to improve a brightness not only at an upper surface but also at side surfaces of a resin sealant covering the light emitting element, thereby providing a high brightness level in a wider range of angle. This light emitting diode comprises a substrate 22, a pair of electrodes 23a, 23b provided on the substrate, a light emitting element 24 mounted on the substrate and electrically connected to the electrodes, a sealant 26 provided on the substrate to seal the electrodes 23a, 23b and the light emitting element 24; and a light scattering layer 30 formed on an outermost layer of a light projecting surface 27 of the sealant 26.

Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.

Abstract: A tunnel diode has a quantum well having at least one layer of semiconductor material. The tunnel diode also has a pair of injection layers on either side of the quantum well. The injection layers comprise a collector layer and an emitter layer. A barrier layer is positioned between each of the injection layers and the quantum well. The quantum well has an epitaxial relationship with the emitter layer. An amount of one element of the well layer is increased to increase the lattice constant a predetermined amount. The lattice constant may have a reduction in the conduction band energy. A second element is added to the well layer to increase the conduction band energy but not to change the lattice constant. By controlling the composition in this matter, the negative resistance, and thus the effective mass, may be controlled for various diode constructions.

Abstract: A vertical type MOSFET and a manufacturing method thereof, in which its drift resistance is made to be low by securing its breakdown voltage between source and drain electrodes of about 150 V being the middle class breakdown voltage and its manufacturing method is easy and its manufacturing cost is low, are provided. At a vertical type MOSFET, in which an N type high resistance drift layer is formed on an N type substrate and P type base layers are formed in designated regions of the surface of the high resistance drift layer and N type source layers are formed in the base layers and gate electrodes are formed on specified regions of the surface of the high resistance drift layer, a trench type back gate section is formed in a trench positioned at a region between the gate electrodes, by filling a insulation material in the trench.

Abstract: A semiconductor device includes a lower wiring layer, a first insulating layer formed on the lower wiring layer and having a via hole with a width, a via mask layer formed on the first insulating layer and having an opening with a width larger than the width of the via hole, a second insulating layer formed on the via mask layer and having an upper wiring, groove whose width coincides with the width of the via hole, a via contact structure buried in the via hole, and an upper wiring layer buried in the upper wiring groove.

Abstract: A filter for filtering micro-emboli from a patient's blood during an angioplasty procedure is disclosed which comprises a plurality of curved wires connected to a rod between a first connector fixed with respect to the rod and a second connector slidingly mounted on the rod. Two layers of filter material are connected to opposite sides of the wires, and each layer includes perforations which are offset from the perforations in the other layer. When the rod and the wires are disposed within a catheter, the inner wall of the catheter compresses the wires toward the rod and when the rod is extended from the catheter, the wires resume their curved shape and pull the sliding connector along the rod toward the fixed connector.

Abstract: A MOSFET structure comprises a tortuous gate having a first sidewall and a second sidewall, disposed over a semiconductor substrate. A source region is disposed within the semiconductor substrate adjacent to the first sidewall of the tortuous gate. The source region comprises a broader part and a narrower part. Contacts are positioned above the broader part of the source region and are in contact with the broader part of the source region. A drain region is disposed within the semiconductor substrate adjacent to the second sidewall of the tortuous gate. The drain region comprises a broader part and a narrower part. Contacts are disposed above the broader part of the drain region and are in contact with the broader part of the drain region. The broader part of the drain region is disposed opposite to the narrower part of the source region. The narrower part of the drain region is disposed opposite to the broader part of the source region.

Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the Created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.