Patents Examined by Hoa Nguyen
  • Patent number: 6484214
    Abstract: A method for acquiring and assembling software components at execution time into a client program, where the components may be acquired from remote networked servers is disclosed. The acquired components are assembled according to knowledge represented within one or more acquired mediating components. A mediating component implements knowledge of an object model. A mediating component uses its implemented object model knowledge, acquired component class information and polymorphism to assemble components into an interacting program at execution time. The interactions or abstract relationships between components in the object model may be implemented by the mediating component as direct invocations or indirect events or software bus exchanges. The acquired components may establish communications with remote servers. The acquired components may also present a user interface representing data to be exchanged with the remote servers.
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: November 19, 2002
    Assignee: McDonnell Douglas Helicopter Company
    Inventor: Amy Sundermier
  • Patent number: 6466991
    Abstract: A method for data communication between objects or between object-oriented programming systems, such as object-oriented operating systems (OS), in which transparency to different environments is presented for convenience to a programmer. In the data communication method for having communication between the object-oriented operating systems or between objects, a tag (Tag), a future (Future) and continuation (Continuation) are handled as a tag (Tag) for controlling the synchronization and parallelism of communication between objects proper to different communication mechanisms having different properties or interfaces. These tags are communicated along with the communication message.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: October 15, 2002
    Assignee: Sony Corporation
    Inventors: Koichi Moriyama, Seiji Murata
  • Patent number: 6421704
    Abstract: A system for leasing a group membership in a distributed processing system is provided. In accordance with this system, a remote object requests from an activation group a membership in the activation group for a period of time. Responsive to this request, the activation group determines an appropriate lease period during which time the remote object becomes a member of the activation group and runs in the same address space as other objects of the activation group.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: July 16, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: James H. Waldo, Ann M. Wollrath, Robert Scheifler, Kenneth C. R. C. Arnold
  • Patent number: 6370590
    Abstract: According to an approach for providing communication between sub-applications in a vertical application, messages transmitted by sub-applications in message formats supported by the sub-applications are translated to produce messages in a predetermined common message format referred to herein as a “common view.” Messages to be received by sub-applications in the common view are translated to produce messages in the formats supported by the sub-applications. An adapter attached to each sub-application provides for the translation of messages between a message format supported by the sub-application to which it is attached and the common view.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: April 9, 2002
    Assignee: Oracle Corporation
    Inventors: David Nitz, Dave McBride
  • Patent number: 6349321
    Abstract: A central processing unit schedules the start time of a following special process based on the progress status of a preceding special process being executed in an auxiliary processing unit and the processing time and the end time of the following special process.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: February 19, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Isao Katayama
  • Patent number: 6226789
    Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: May 1, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Steven Tony Tye, John S. Yates
  • Patent number: 6223202
    Abstract: A technique, system, and computer program for enabling multiple virtual machines to execute on a single server, using virtual machine pooling. This will result in a more scalable network environment, increasing the processing capacity of the server and decreasing the amount of time a particular request waits before being processed. Further, the integrity of an application's data will be protected from inadvertent overwriting by another application, because each application can be running in a separate virtual machine. Garbage collection, crashes, and hangs will no longer temporarily or completely halt a server: when one virtual machine halts, others can continue executing. Multiple environments can now execute on a single server, including different versions of virtual machines, increasing the mix of servlets that can be supported. Further, debugging can now occur concurrently with normal application execution, by isolating the debugging function to a specific virtual machine.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: April 24, 2001
    Assignee: International Business Machines Corp.
    Inventor: Elias Naji Bayeh
  • Patent number: 6161194
    Abstract: A storage data reconstruction system including a plurality of storage units for storing therein divided data, the plural independent storage units forming a set; units for storing therein ECC data corresponding to the divided data; a spare storage unit for storing therein reconstructed data; an I/O-reconstruction control circuit; a timer; a data reconstructing table for a storage unit which has failed and a circuit for reconstructing faulty data. When a failure occurs in any of the storage units, the failure is detected by an error check, a state of the failure is discriminated, a preferred processing suitable for the state of the failure is selected from a processing of a normal access or read/write, and a data reconstruction processing, and the selected processing is carried out, or the frequency of the processing of the normal access or read/write and the data reconstruction processing, or the ratio of the amount of the data reconstruction processing within a unit time, is set.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: December 12, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Tanaka, Yoshihisa Kamo, Hitoshi Kakuta
  • Patent number: 6134686
    Abstract: A method and apparatus comprising (i) a first circuit that may be configured to generate a first and second pulse in response to a reset signal, (ii) a latch circuit that may be configured to generate a first and second latch output in response to (a) the first and second pulses, (b) the reset signal and (c) an input signal and (iii) a third circuit that may be configured to generate a detect output in response to the first and second latch outputs. The detect output may be implemented as a trigger signal having an enabled state indicating a floating voltage is present on the input signal. The first and second latch outputs may be used to indicate the drive strength of the input signal. The enabled state of the detect output may have a floating state other than a standard logic "1" or logic "0".
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: October 17, 2000
    Assignee: Cypress Semiconductor Corp.
    Inventor: Kaushal Kumar Jha
  • Patent number: 6122762
    Abstract: An integrated circuit memory interface device includes a debug controller for generating debug control signals in response to memory access control signals, and individual address and data boundary-scan registers. Each of the address and data boundary-scan registers has a predetermined number of cells which are daisy-chained from cell to cell. The address and data registers are placed between a memory device and a core logic which performs normal interface operations with respect to the devices during a normal mode. The interface device includes a test access port (TAP) controller which operates in synchronism with a test clock signal during test and debugging modes, and an instruction register. The TAP controller receives a test mode select signal and generates register control signals in response to the test clock and mode select signals.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: September 19, 2000
    Assignee: Samsung Electronics Co., LTD
    Inventor: Ho-Ryong Kim
  • Patent number: 6073261
    Abstract: The present invention is generally directed to a circuit and method for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with one aspect of the invention, a circuit is provided having a signal select circuit that is includes two or more inputs and one output. The signal select circuit (preferably a multiplexer) is configured to select one of the two or more input signals for evaluation and direct it to the output. A plurality of signal buffers are electrically cascaded to the output of the signal select circuit. Finally, a scan chain having a plurality of scan elements is disposed to acquire a state of electrical signals along the plurality of signal buffers. In accordance with another aspect of the invention, a method is provided for evaluating the timing relationship of electrical signals in an integrated circuit.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: June 6, 2000
    Assignee: Hewlett Packard Company
    Inventor: Brian C. Miller
  • Patent number: 6032275
    Abstract: It is to provide a test pattern generator that can easily generate expected value data for arbitrary initial values when testing a memory device having a function of write enable/disable control per bit. The pattern generator includes an XOR controller (131) which generates a control signal in response to instructions from an instruction memory (112), an AND gate which receives an output signal of the XOR controller (131) at its one terminal and an inverted output signal of a data generator B (15) at its other input terminal, and an exclusive OR gate (121) which receives an output of the AND gate (123) at its one input terminal and an output a data generator A (14) at the other input terminal.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: February 29, 2000
    Assignee: Advantest Corp.
    Inventor: Masaru Tsuto
  • Patent number: 5539878
    Abstract: A method for testing CPU microprocessors having internal cache involves testing one IU and a portion of the internal cache, then loading a cache test routine to the tested portion of internal cache and causing that routine to be executed by the tested IU to test the previously untested portion of the internal cache while simultaneously testing any other IUs and circuitry on the CPU microprocessor. A system is disclosed for performing the method.
    Type: Grant
    Filed: June 16, 1995
    Date of Patent: July 23, 1996
    Assignee: Elonex Technologies, Inc.
    Inventor: Dan Kikinis
  • Patent number: 5479414
    Abstract: Algorithmically generated test patterns are structured for efficient test of "scan path" logic devices. A look ahead pattern generation and simulation scheme achieves a pre-specified fault coverage. The fault simulation engine picks one of two paths at the end of each Tester Loop (TL) simulation: (1) restore to the state just prior to the current simulated Tester Loop and advance the pattern generators one state if an ineffective Tester Loop was found or (2) advance the pattern generators one state (from the end of the Tester Loop) if an effective Tester Loop was encountered. This basic technique can be modified to support parallel fault simulation by defining the pattern generator state at the start of the next tester loop (TL) state (TL.sub.n+1) to be one state advanced from the pattern generator state at the START of TL.sub.n. The pattern generator state for the start of all future TLs can be determined and parallel fault simulation is supported.
    Type: Grant
    Filed: March 7, 1994
    Date of Patent: December 26, 1995
    Assignee: International Business Machines Corporation
    Inventors: Paul N. Keller, Timothy J. Koprowski
  • Patent number: 5430746
    Abstract: A method of and a circuit arrangement for detecting synchronization of two word sequences between a measurement signal and a reference signal. The signals are applied to an exclusive OR-gate comparator whose output produces an error signal which is compared with an error signal shifted by one period. This comparison is effected by an exclusive OR-gate and in the case of coincidence, indicating that the measurement and reference signals are phase-shifted, a new synchronization is enabled. The output of the exclusive OR-gate is an error signal which is time-shifted in a shift register and multiplexer so that the time shifted bit sequence is compared with the bit sequence of the first error signal in a second exclusive OR-gate which is connected to an AND-gate for detecting coincidence and generating a further synchronization signal which is processed through counters, another AND-gate and a flip-flop to produce the synchronization signal which is applied to the reference pattern generated.
    Type: Grant
    Filed: November 8, 1993
    Date of Patent: July 4, 1995
    Assignee: Wandel & Goltermann GmbH & Co. Elektronische Messtechnik
    Inventor: Gunter Renz
  • Patent number: 5420870
    Abstract: An address count which increases up to, or decreases down from, a user-selected value is generated by a non-fully-decoded address generator (10) which is configured of a plurality of interconnected, sequentially-actuated of bit generators (12'.sub.1 -12'.sub.k), each generating a separate one of the bits of the address count. Each of the bit generators is presettable to at least one logic state, with at least one bit generator being presettable to a separate one of two logic states. A control circuit (30' presets the bit generators in accordance to the user-selected initial value so that when the bit generators are sequentially actuated, their collective count runs up to, or down from, the seed value.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: May 30, 1995
    Assignee: AT&T Corp.
    Inventor: Ilyoung Kim
  • Patent number: 5283891
    Abstract: An error information saving apparatus of a computer includes at least one arithmetic unit, a plurality of storage units, and a control unit, connected to the storage units and the arithmetic unit, for controlling these units to perform a predetermined pipeline operation, wherein the storage units comprise an arithmetic register file consisting of a plurality of registers each of which can be designated as a destination operand in a statement of an operation instruction, a status flag string consisting of a plurality of flags provided in a one-to-one correspondence with the registers of the arithmetic register file, and a destination register number holding unit for sequentially saving and holding the numbers of destination registers of all operations performed while error interrupt processing generated after occurrence of an error is delayed by a predetermined time interval, each time one of the operations is completed.
    Type: Grant
    Filed: August 7, 1992
    Date of Patent: February 1, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichiro Suzuki, Yoichiro Takeuchi, Ikuo Uchihori, Tadashi Ishikawa, Ryuji Sakai
  • Patent number: 5282095
    Abstract: A magneto-optical recording medium on which new information can be directly over-written over pre-existing recorded information. Such medium comprises two magneto-optical recording layers which have a difference in Curie temperature in the range of 0.degree. C. -25.degree. C. and which are separated from each other by a metal layer for the transfer of heat, such as aluminum. Recording is effected by scanning the medium with a write spot produced by a pulsed laser beam concurrently with application of an external magnetic field which is modulated in accordance with the information to be recorded. The layers may have equal Curie temperatures if they behave thermally asymmetrically. At any scanning position of the write spot the scanned superposed local areas of the two recording layers are heated thereby above the Curie temperature of at least one of such layers and then permitted to cool while being subjected to the external magnetic field.
    Type: Grant
    Filed: March 17, 1992
    Date of Patent: January 25, 1994
    Assignee: U.S. Philips Corporation
    Inventors: Johannes H. M. Spruit, Bernardus A. J. Jacobs
  • Patent number: 5267224
    Abstract: An improved liquid crystal device such as an optical disc memory or a display device with a ferroelectric liquid crystal (FLC) is shown. As FLC a chiral smectic liquid crystal is employed to exhibit a hysteresis between a pair of substrates which have easy polarization axes normal to each other. Information to be recorded are written on the disc in terms of a binary system by use of the hysteresis. A ferroelectric layer contiguous to the liquid crystal makes the nonvolatility of the memory sure.
    Type: Grant
    Filed: June 18, 1991
    Date of Patent: November 30, 1993
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 5253233
    Abstract: A method of making a magneto-optical recording medium for having information magnetically recorded on its recording layer read out by magneto-optical effect by applying a reproducing light beam emitted from a semiconductor laser thereto and detecting the reflected light beam thereof by means of a photodetector having no self-multiplication characteristic or a photodetector having a self-multiplication characteristic. The method includes the steps of selecting a recording layer comprising a magnetic film; selecting a light interference layer comprising a dielectric; defining the thickness of the light interference layer by: ##EQU1## where d is the film thickness of the light interference layer, N is the refractive index of the light interference layer and .lambda. is the wavelength of the reproducing light, Y is selected from 0, 1 and 2, and 1.ltoreq.X.ltoreq.3 or 5.ltoreq.X.ltoreq.7 in the first case or 2.ltoreq.X.ltoreq.3.9 or 4.1.ltoreq.X.ltoreq.
    Type: Grant
    Filed: August 28, 1991
    Date of Patent: October 12, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventor: Eiichi Fujii